NDLI: IO Standard based low power memory design and implementation on FPGA

Content Provider	IEEE Xplore Digital Library
Author	Kaur, R. Kumar, J. Nagah, S. Pandey, B. Goswami, K.
Copyright Year	2015
Description	Author affiliation: Nat. Knowledge Network Lab., Indian Inst. of Inf. Technol., Gwalior, India (Kumar, J.) \|\| Dept. of CSE, Panjab Univ., Chandigarh, India (Kaur, R.) \|\| Gyancity Res. Lab., New Delhi, India (Nagah, S.; Pandey, B.; Goswami, K.)
Abstract	In this work of low power memory design on FPGA, we are using the most energy efficient I/O standard among LVCMOS, HSLVDCI, HSTL, LVDCI_DV2 and SSTL. I/O standard is used to match impedance of transmission line, impedance of port and impedance of memory for avoidance of transmission line reflection. In naming convention of I/O Standard, LV is Low Voltage, HS is High Speed, DV2 is Half Impedance, CMOS is Complementary Metal Oxide Semiconductor, DCI is Digitally Control Impedance and SSTL is Stub Series Transistor Logic. We are saving 94.28%, 94.26%, 32% power with LVCMOS in place of SSTL, HSTL, and HSLVDCI respectively. We are also saving 95.29%, 95.27%, 44%, 17.65% power using LVDCI_DV2 in comparison to SSTL, HSTL, HSLVDCI and LVCMOS respectively. Xilinx Planahead 13.4 and Xilinx Power 13.4 is used as simulator in order to synthesize, simulate, and implement low power RAM-UART memory interface design on this FPGA. XPower analyzer is used for power analysis.
Starting Page	1501
Ending Page	1505
File Size	1018336
Page Count	5
File Format	PDF
ISBN	9789380544151
e-ISBN	9789380544168
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-03-11
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Bharati Vidyapeeth University, New Delhi
Subject Keyword	HSTL Output Drive Voltage FPGA Random access memory Standards Low voltage IO Standard LVCMOS Energy efficiency Impedance Field programmable gate arrays SSTL Clocks LVDCI Low Power RAM
Content Type	Text
Resource Type	Article

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