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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ang Lay Sean Rosdi, B.A. Tee Kok Tiong |
| Copyright Year | 2011 |
| Description | Author affiliation: Intel Corporation, Penang, Malaysia (Tee Kok Tiong) || Universiti Sains Malaysia (USM), Intel Corporation, Penang, Malaysia (Ang Lay Sean) || Universiti Sains Malaysia (USM), Penang, Malaysia (Rosdi, B.A.) |
| Abstract | As design size gets larger and becomes more complicated with feature integration, the runtime for Static Timing Analysis (STA) becomes more of a concern. Due to time-to-market pressure, the validation of the design is performed in parallel with the physical synthesis flow; therefore it is not uncommon to find last minute critical logic bugs during final design integration iterations. However, timing verification needs to be run on full-chip level to ensure that the check is comprehensive. This paper proposes a method to isolate only those logics which are affected by the Engineering Change Order (ECO) for STA. This simplification will allow faster ECO iteration to enable a more efficient timing convergence. The proposed method is also suitable to be used for multithreading in STA engines to speed-up timing verification due to ECO changes. Engineering Change Order (ECO), Static Timing Analysis (STA), Incremental Static Timing Analysis, VLSI design |
| Starting Page | 267 |
| Ending Page | 272 |
| File Size | 298985 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781457714184 |
| e-ISBN | 9781457714177 |
| DOI | 10.1109/ISIEA.2011.6108713 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-09-25 |
| Publisher Place | Malaysia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Integrated circuit interconnections Logic gates Capacitance Pins Data mining Delay |
| Content Type | Text |
| Resource Type | Article |
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