NDLI: Integration of intra chip stack fluidic cooling using thin-layer solder bonding

Content Provider	IEEE Xplore Digital Library
Author	Madhour, Y. Zervas, M. Schlottig, G. Brunschwiler, T. Leblebici, Y. Thome, J.R. Michel, B.
Copyright Year	2013
Description	Author affiliation: Microelectron. Syst. Lab., EPFL LSM, Lausanne, Switzerland (Zervas, M.; Leblebici, Y.) \|\| Heat & Mass Transfer Lab. (LTCM), EPFL, Lausanne, Switzerland (Madhour, Y.; Thome, J.R.) \|\| IBM Res. - Zurich, Rüschlikon, Switzerland (Schlottig, G.; Brunschwiler, T.; Michel, B.)
Abstract	Three-dimensional (3D) stacking of integrated-circuit (IC) dies by vertical integration increases system density and package functionality. The vertical integration of IC dies by area-array Through-Silicon-Vias (TSVs) reduces the length of global interconnects and accordingly the signal delay time. On the other hand, the ongoing miniaturization trend of ICs results in constantly increasing chip-level power densities. Thus, the development of new chip cooling concepts is of utmost importance. Therefore, scalable cooling solutions for chip stacks, such as interlayer cooling, need to be investigated. This paper presents a new concept for the integration of intra chip stack fluidic cooling, namely die-embedded microchannels for single- and two-phase thermal management, using a patterned thin-layer eutectic solder bonding technique for the stack assembly. Results showed the successful fabrication of 5-layer chip stacks with embedded microchannels and high aspect ratio TSVs. Optical inspections demonstrated the proper bond line formation and direct current (DC) daisy-chain electrical tests indicated the successful combination of TSVs with thin-layer solder interconnects. Mechanical shear tests on die-on-die bonded samples showed the strength of the patterned thin-layer solder bond (16MPa). An added solder ring-pad component to seal the electrically active pad from any conductive liquid coolant was also investigated and reflow tests on such geometries showed the appearance of a balling effect along the solder ring line. This balling was found to be mitigated when the ring aspect ratio (deposited solder height to ring width ratio) was kept below the experimentally observed critical value of 0.65.
Sponsorship	IEEE Components, Pack., Manuf. Technol. Soc.
Starting Page	1
Ending Page	8
File Size	1299832
Page Count	8
File Format	PDF
ISBN	9781467364843
DOI	10.1109/3DIC.2013.6702343
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Cooling Thin-layer solder bonding Microchannel TSV Interlayer chip cooling Silicon Electrical resistance measurement Bonding Through-silicon vias Solder sealing ring 3D stacking
Content Type	Text
Resource Type	Article

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