NDLI: A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns

Content Provider	IEEE Xplore Digital Library
Author	Weldezion, A.Y. Grange, M. Pamunuwa, D. Jantsch, A. Tenhunen, H.
Copyright Year	2013
Description	Author affiliation: Electron. Syst., KTH R. Inst. of Technol., Kista, Sweden (Weldezion, A.Y.; Jantsch, A.; Tenhunen, H.) \|\| Calibre Div., Mentor Graphics, Wilsonville, OR, USA (Grange, M.) \|\| Dept. Electr. & Electron. Eng., Univ. of Bristol, Bristol, UK (Pamunuwa, D.)
Abstract	This paper describes a powerful simulation platform that enables accurate simulations of numerous network configurations under realistic traffic patterns to predict the performance and power needs of a 3-D integrated system early in the design flow. The simulation platform can model virtually any sized 2-D or 3-D network configuration, providing low-cost and fast tradeoff evaluations of various systems architectures. The network simulator uses scalable RTL-level models that can be used for accurate power and timing analyses. We demonstrate the capability of our simulation model by analyzing the performance of various network topologies under spatio-temporal traffic patterns to show how the network topology can be adjusted to meet the performance requirements of a design before it is manufactured. The simulation results can be used to optimize the placement of cores and communication buses early in the flow. By using the model, standard applications such as mobile application processor, femto-cell base-stations on-chip and wide-IO TSV memory stacking can be simulated.
Sponsorship	IEEE Components, Pack., Manuf. Technol. Soc.
Starting Page	1
Ending Page	5
File Size	466424
Page Count	5
File Format	PDF
ISBN	9781467364843
DOI	10.1109/3DIC.2013.6702365
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Solid modeling Analytical models System-on-chip Data mining Through-silicon vias Integrated circuit modeling Monitoring
Content Type	Text
Resource Type	Article

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