NDLI: Power flip-chip assembly for space application using HBT in Ku band

Content Provider	IEEE Xplore Digital Library
Author	Vendier, O. George, S. Fraysse, J.-P. Rogeaux, E. Drevon, C. Cazaux, J.-L. Floriot, D. Caillas-Devignes, N. Blanck, H. Doser, W. Auxemery, P. de Ceuninck, W. Petersen, R. Haese, N. Rolland, P.-A.
Copyright Year	2000
Description	Author affiliation: Alcatel Espace, Toulouse, France (Vendier, O.)
Abstract	Flip-chip assembly using pure Au-Au thermocompression process have been implemented for use in power HBT. Thermal path optimization has conducted to measure 30% decrease of thermal resistance of flip-chip mounted HBT compared to face up mounted. In best configuration (thermal bump on top of emitter finger) it is anticipated to reach 40% decrease. First demonstration of this technology has been done on HBT single devices. It is shown that no electrical degradation occurred after thermocompression even after an aging of 300 thermal cycle (55/spl deg/C, +125/spl deg/C). Further validation will be done through high power amplifier design, fabrication and test with simulated performances of 2.5 W output power in Ku band, 19 dB linear gain and over 35% power added efficiency.
Starting Page	157
Ending Page	159
File Size	401478
Page Count	3
File Format	PDF
ISBN	0780359682
ISSN	10647775
DOI	10.1109/GAAS.2000.906313
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High power amplifiers Thermal resistance Fingers Aging Thermal conductivity Heterojunction bipolar transistors Electrical resistance measurement Assembly Electric resistance Thermal degradation
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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