NDLI: A low power 72.8 GHz static frequency divider implemented in AlInAs/InGaAs HBT IC technology

Content Provider	IEEE Xplore Digital Library
Author	Sokolich, M. Fields, C. Shi, B. Brown, Y.K. Montes, M. Martinez, R. Kramer, A.R. Madhav, M.
Copyright Year	2000
Description	Author affiliation: HRL Labs., Malibu, CA, USA (Sokolich, M.)
Abstract	We report a 72.8 GHz fully static frequency divider in AlInAs/InGaAs HBT IC technology. The CML divider operates with a 350 mV logic swing at less than 0 dBm input power up to a maximum clock rate of 63 GHz and requires 86 dBm of input power at the minimum clock rate of 72.8 GHz. Power dissipation per flip-flop is 55 mW with a 3.1 V power supply. To our knowledge this is the highest frequency of operation for a static divider in any technology. The power-delay product of 94 fJ/gate is also the lowest power-delay product for a circuit operating above 50 GHz in any technology. A low power divider on the same substrate operates at 36 GHz with 6.9 mW of dissipated power per flip-flop with a 3.1 V supply. The power delay of 24 fJ/gate is, to our knowledge, the lowest power delay product for a static divider operating above 30 GHz in any technology.
Starting Page	81
Ending Page	84
File Size	408435
Page Count	4
File Format	PDF
ISBN	0780359682
ISSN	10647775
DOI	10.1109/GAAS.2000.906297
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power supplies Circuits Frequency conversion Indium gallium arsenide Heterojunction bipolar transistors Power dissipation Logic Delay Clocks Flip-flops
Content Type	Text
Resource Type	Article

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