NDLI: Tri-gate poly-Si thin-film transistor with nanowire channels

Content Provider	IEEE Xplore Digital Library
Author	Hsing-Hui Hsu Homg-Chih Lin Tiao-Yuan Huang
Copyright Year	2008
Description	Author affiliation: Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan (Hsing-Hui Hsu; Homg-Chih Lin; Tiao-Yuan Huang)
Abstract	The fine grain structure of poly-Si thin-film transistor (poly-Si TFT) is known to affect the carrier transport and device performance. Various methods have been proposed to increase the grain size of poly-Si thin films, including excimer laser annealing (ELA) and metal-induced lateral crystallization (MILC), in order to improve device characteristics. An alternative approach for minimizing the negative impacts of poly-Si film is to reduce the total amount of defects by thinning down the channel body. In line with this, the adoption of a multiple-gated (MG) nanowire (NW) structure is promising. The MG configuration can further improve the performance of poly-Si TFT devices through enhanced gate controllability over the channel. In this work, we propose a new fabrication scheme for poly-Si NW formation. Poly-Si TFTs with ultra-thin NW channels and tri-gated configuration are demonstrated and characterized. Moreover, a multiple-channel layout scheme is proposed to multiply the device drive current while minimizing the device layout area.
Starting Page	1
Ending Page	2
File Size	2067364
Page Count	2
File Format	PDF
ISBN	9781424420711
DOI	10.1109/SNW.2008.5418410
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fabrication Grain size Wet etching Plasma applications Annealing Thin film devices Crystallization Controllability Thin film transistors Nanostructures
Content Type	Text
Resource Type	Article

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