NDLI: Switching losses analysis in MHz integrated synchronous Buck converter to support optimal power stage width segmentation in CMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Xiaopeng Wang Jinseok Park Van Brunt, E.R. Huang, A.Q.
Copyright Year	2010
Description	Author affiliation: On Semiconductor Corp., 5005 East McDowell Road, Phoenix, AZ. 85008, USA (Jinseok Park) \|\| NSF FREEDM Systems Center, North Carolina State University, 1017 Main Campus Drive, Suite 2100, Raleigh, 27695, USA (Xiaopeng Wang; Van Brunt, E.R.; Huang, A.Q.)
Abstract	Power stage width segmentation has been verified to be effective to improve the efficiency of MHz integrated synchronous Buck converters (ISBC). However, the theoretical analysis of the relationship between the load current and the power stage width or the number of active baby cells had not yet been established. This paper suggests a breakdown analysis of the transient currents in power FETs and recommends one kind of physical based separation between charging/discharging loss and overlap loss. Furthermore, criteria of the Miller plateau are presented to interpret the difference about overlap loss between the control PFET turning on and off. Moreover, five typical types of energy dissipations due to the charging/discharging process of the parasitic capacitors in power FETs are classified so that the charge/discharge losses in four different switching events can be separately evaluated. On the basis of the aforementioned concepts and analysis, the number of the active baby cells necessary for the optimal power stage segmentation in an example ISBS for portable application can be theoretically predicted. The derived values match well with the simulation results.
Starting Page	2718
Ending Page	2724
File Size	996960
Page Count	7
File Format	PDF
ISBN	9781424452866
DOI	10.1109/ECCE.2010.5618055
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitors Power conversion efficiency Switches Turning DC-DC synchronous Buck converter Power stage width segmentation Inductors Integrated circuits Switching loss Miller Plateau CMOS technology Transient analysis FETs Parasitic capacitance
Content Type	Text
Resource Type	Article

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