NDLI: Design of a new split-capacitive-array DAC based on distribution of attenuation capacitor

Content Provider	IEEE Xplore Digital Library
Author	Nazari, M. Aghajani, A. Hashemipour, O.
Copyright Year	2015
Description	Author affiliation: Fac. of Electr. & Comput. Eng., Shahid Beheshti Univ., Tehran, Iran (Nazari, M.; Aghajani, A.; Hashemipour, O.)
Abstract	In this paper, a new split capacitive array digital to analog converter (DAC) with the advantage of capacitor area reduction is presented. In more details, the attenuation capacitor of the conventional split array DAC is distributed to achieve small integral nonlinearity (INL) and differential nonlinearity (DNL) errors, low glitch energy, small capacitor mismatches, high speed and small chip area. To compare this work with conventional structures, an 8-bit DAC with the proposed configuration in 0.18μm CMOS technology is designed. Simulation results show that 47% reduction in the value of capacitors is achieved and spurious-free dynamic range (SFDR) of the proposed configuration at 40 MS/s is 6 dB better than the conventional structure for various frequencies of sinusoidal input signal. In addition, total power consumption of the designed DAC is 760 μWatt and more accurate operation is obtained.
Starting Page	1370
Ending Page	1373
File Size	717267
Page Count	4
File Format	PDF
e-ISBN	9781479919727
DOI	10.1109/IranianCEE.2015.7146431
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-10
Publisher Place	Iran
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electrical engineering Decision support systems Attenuation capacitor Split capacitive array DAC Small differential nonlinearity Conferences Low glitch energy High speed Capacitor area reduction Registers Approximation methods Small capacitor mismatches
Content Type	Text
Resource Type	Article

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