NDLI: Design of CAD ASIP for JIT extensible processor: Case study on PathFinder routing algorithm

Content Provider	IEEE Xplore Digital Library
Author	Daryanavard, H. Eshghi, M. Jahanian, A.
Copyright Year	2015
Description	Author affiliation: Shahid Beheshti Univ., Tehran, Iran (Daryanavard, H.; Eshghi, M.; Jahanian, A.)
Abstract	Just-In-Time (JIT) Extensible Processor is the most flexible platform among others reconfigurable computing platforms. In this platform all computing intensive kernels can be translated to bitstream by embedded CAD processor to be executed on hardware part. Executing CAD algorithms on embedded processor is a time-consuming task and normally is not feasible for real user applications. In this paper, the design of an application-specific instruction set processor (ASIP) has been proposed as a promising solution to speed up the execution time of CAD algorithm used in JIT extensible processor. The proposed ASIP is customized for routing which is one of most time consuming phases. Simplescalar simulator toolset is used to provide high flexible performance processor architecture and adding new extracted instruction set and customized register file and memory to processor. Regarding this specification, we achieved 10X speedup for routing phases.
Starting Page	1322
Ending Page	1326
File Size	691601
Page Count	5
File Format	PDF
e-ISBN	9781479919727
DOI	10.1109/IranianCEE.2015.7146421
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-10
Publisher Place	Iran
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decision support systems Electrical engineering Simplescalar Application Specific Instruction Set Processor Design automation Just-In-Time Extensible Processor Conferences PathFinder Routing Wires Routing Field programmable gate arrays
Content Type	Text
Resource Type	Article

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