NDLI: A wide-range DC/DC converter with $2^{nd}$ order digital compensation and direct battery connection in 40nm CMOS

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2015 IEEE Custom Integrated Circuits Conference (CICC)

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2011 IEEE Custom Integrated Circuits Conference (CICC)

Steering committee

Educational session 1

Table of contents

Welcome from the CICC committee

A fully integrated highly linear efficient power amplifier in 0.25µm BiCMOS technology for wireless applications

A 1.9/2.4GHz dual band CMOS power amplifier with integrated AM-PM distortion canceller

Managing linearity in radio front-ends

A transformer-based broadband I/O matching-balun-T/R switch front-end combo scheme in standard CMOS

A low conversion loss passive frequency doubler

An 18µW 79dB-DR 20KHz-BW MASH ΔΣ modulator utilizing self-biased amplifiers for biomedical applications

A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW

A 1-1-1-1 MASH delta-sigma modulator using dynamic comparator-based OTAs

A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application

A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer

A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay

A 3.6GS/s, 15mW, 50dB SNDR, 28MHz bandwidth RF ΔΣ ADC with a FoM of 1pJ/bit in 130nm CMOS

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons

A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm

Smart integrated temperature sensor - mixed-signal circuits and systems in 32-nm and beyond

ReSSP: A 5.877 TOPS/W Reconfigurable Smart-camera Stream Processor

3.6-GHz 0.2-mW/ch/GHz 65-nm cross-correlator for synthetic aperture radiometry

Understanding the Antikythera Mechanism

Timing inaccuracy of clocks

Frequency reference challenges - a systemic view

A dither-less all digital PLL for cellular transmitters

A 0.5-V, 440-µW frequency synthesizer for implantable medical devices

A 4-GHz all digital fractional-N PLL with low-power TDC and big phase-error compensation

A quadrature LO generator using bidirectionally-coupled oscillators for 60-GHz applications

A 0.6V quadrature VCO with optimized capacitive coupling for phase noise reduction

A combined VCO and divide-by-two for low-voltage low-power 1.6 GHz quadrature signal generation

A 2.2GHz PLL using a phase-frequency detector with an auxiliary sub-sampling phase detector for in-band noise suppression

A fractional-N frequency synthesizer using high-OSR delta-sigma modulator and nested-PLL

A sub-100µW 2GHz differential colpitts CMOS/FBAR VCO

A 60mW 1.15mA/channel Class-G Stereo Headphone Driver with 111dB DR and 120dB PSRR

A multi-GHz area-efficient comparator with dynamic offset cancellation

Zero-pole modulation and demodulation for noise reduction in charge amplifiers

Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs

Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs

Characterization of SRAM sense amplifier input offset for yield prediction in 28nm CMOS

Design challenges for prototypical and emerging memory concepts relying on resistance switching

A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias

Improved circuits for microchip identification using SRAM mismatch

Circuit technologies for mm-wave wireless systems on silicon

A 76-81GHz transmitter with 10dBm output power at 125 °C for automotive radar in 65nm bulk CMOS

A 2.9-dB noise figure, Q-band millimeter-wave CMOS SOI LNA

A high gain 107 GHz amplifier in 130 nm CMOS

Double-balanced 130–180 GHz passive and balanced 145–165 GHz active mixers in 45 nm CMOS

60GHz low-loss compact phase shifters using a transformer-based hybrid in 65nm CMOS

A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for biomedical applications

A 0.7V 810µW 10b 30MS/s comparator-based two-step pipelined ADC

A 450 MS/s 10-bit time-interleaved zero-crossing based ADC

A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS

Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling

Broadband compact model for on-chip mm-wave transformers and baluns with emphasis on capacitive coupling effects

Bottom-up digital system-level reliability modeling

Wafer-specific centering of compact transistor model parameters for advanced technologies and models

High-dimensional statistical modeling and analysis of custom integrated circuits (invited paper)

Fast and accurate event-driven simulation of mixed-signal systems with data supplementation

Enhanced sensitivity computation for BEM based capacitance extraction using the Schur complement technique

Power gating implementation for noise mitigation with body-tied triple-well structure

Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network

A 90nm data flow processor demonstrating fine grained DVS for energy efficient operation from 0.25V to 1.2V

An integrated four-phase buck converter delivering $1A/mm^{2}$ with 700ps controller delay and network-on-chip load in 45-nm SOI

A wide-range DC/DC converter with $2^{nd}$ order digital compensation and direct battery connection in 40nm CMOS

An 80% peak efficiency, 0.84mW sleep power consumption, fully-integrated DC-DC converter with buck/LDO mode control

Perturbation on-time (POT) control and inhibit time control (ITC) in suppression of THD of power factor correction (PFC) design

A reconfigurable 2× / 2.5× / 3× / 4× SC DC-DC regulator for enhancing area and power efficiencies in transcutaneous power transmission

A near-zero cross-regulation single-inductor bipolar-output (SIBO) converter with an active-energy-correlation control for driving cholesteric-LCD

Area efficient phase calibration of a 1.6 GHz multiphase DLL

Digital clock and data recovery circuit design: Challenges and tradeoffs

An all-digital PLL synthesized from a digital standard cell library in 65nm CMOS

An open-loop 10GHz 8-phase clock generator in 65nm CMOS

SAW-less software-defined radio transceivers in 40nm CMOS

A dual-channel GPS/Compass/Galileo/GLONASS reconfigurable GNSS receiver in 65nm CMOS

Complete SOC transceiver in 0.18µm CMOS using Q-enhanced filtering, sub-sampling and injection locking

A wireless sensor node for condition monitoring powered by a vibration energy harvester

Design and technology interaction beyond 32nm

Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs

28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications

Three Dimensional integration - Considerations for memory applications

DRAM-on-logic Stack – Calibrated thermal and mechanical models integrated into PathFinding flow

Test challenges for 3D integration (an invited paper for CICC 2011)

CDM-ESD induced damage in components using stacked-die packaging

Silicon photonics for on-chip interconnections

A 19 mW/lane Serdes transceiver for SFI-5.1 application

A monolithic 3.125 Gbps fiber optic receiver front-end for POF applications in 65 nm CMOS

Addressing link-level design tradeoffs for integrated photonic interconnects

A 7.4 Gb/s forwarded clock receiver based on first-harmonic injection-locked oscillator using AC coupled clock multiplication unit in 0.13µm CMOS

Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS

A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology

Power-efficient I/O design considerations for high-bandwidth applications

Thermal diffusivity sensing: A new temperature sensing paradigm

A self-clocked ASIC interface for MEMS gyroscope with 1m°/s/√Hz noise floor

A 20 µW contact impedance sensor for wireless body-area-network transceiver

256-site active neural probe and 64-channel responsive cortical stimulator

Power management subsystem with bi-directional DC to DC converter for μ-power biomedical applications

A capacitor-based AC-DC step-up converter for biomedical implants

Fully integrated power-efficient AC-to-DC converter design in inductively-powered biomedical applications

Noise and bandwidth performance of single-molecule biosensors

Energy efficient computing in large scale systems

Energy efficient designs with wide dynamic range

Advances and challenges of computing with FPGAs

High-efficient DC-DC converter design

A discrete-time charge-domain filter with bandwidth calibration for LTE application

A new CMOS image sensor readout structure for 3D integrated imagers

All-digital 3-50 GHz ultra-wideband pulse generator for short-range wireless interconnect in 40nm CMOS

A 4GS/s, 8.45 ENOB and 5.7fJ/conversion, digital assisted, sampling system in 45nm CMOS SOI

Energy-efficient transceiver circuits for short-range on-chip interconnects

A novel audio playback chip using digitally driven speaker architecture with 80%@-10dBFS power efficiency, 5.5W@3.3V supply and 100dB SNR

32-nm SOI programmable, high-bandwidth 8.0-GHz digital PLL

A $38.6nV/Hz^{0.5}$ −59.6dB THD dual-band micro-electrode array signal acquisition IC

Analysis and modeling of on-chip power combiners and their losses in LINC transmitters

Programmable phase/frequency generator for system debug and diagnosis using the IEEE 1149.1 test bus

Overlapped inductors and its application on a shared RF front-end in a MultiStandard IC

A true single SoC for UHF mobile RFID reader

A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis

A 1V 13mW frequency-translating ΔΣ ADC with 55dB SNDR for a 4MHz band at 225MHz

CMOS field-modulated color sensor

An 80% peak efficiency, 410mW, single supply rail powered Class-I linear audio amplifier

Band-gap circuit design challenges in high-performance 32-nm technology

Low power and error resilient PN code acquisition filter via statistical error compensation

0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme

An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface

A CMOS image sensor with on-chip motion detection and object localization

Ultra low-FOM high-precision ΔΣ modulators with fully-clocked SO and zero static power quantizers

A Low-Power and low-noise 21∼29 GHz ultra-wideband receiver front-end in 0.18 µm CMOS technology

A fully-integrated optical duobinary transceiver in a 130nm SOI CMOS technology

Electrically-driven retargeting for nanoscale layouts

A partial tree vector quantizer dynamic element matching technique for audio Δ-Σ converters

5 Gbps BPSK CMOS transmitter with on-chip antenna using Gaussian monocycle pulses

Amorphous silicon current steering digital to analog converter

A 65nm CMOS self-terminated open-drain IDAC line driver suitable for fast Ethernet applications

A high-PSR LDO using a feedforward supply-noise cancellation technique

A time-domain latch interpolation technique for low power flash ADCs

Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy

A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition

A 2GHz Digital PLL, with temperature lock range of −40°C to 125°C, in 45nm CMOS

A non-coherent versatile DPSK receiver for high channel-density neural prosthesis

Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS

Indirect phase noise sensing for self-healing voltage controlled oscillators

An at-speed self-testable technique for the high speed domino adder

A 95dB SNDR audio ΔΣ modulator in 65nm CMOS

A fully integrated CMOS nanoscale biosensor microarray

A passive UHF tag for RFID-based train axle temperature measurement system

A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS

Statistical VTH shift variation self-convergence scheme using near threshold VWL injection for local electron injected asymmetric pass gate transistor SRAM

A 5-GS/s 4-bit flash ADC with triode-load bias voltage trimming offset calibration in 65-nm CMOS

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A wide-range DC/DC converter with $2^{nd}$ order digital compensation and direct battery connection in 40nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Shi, J. Ying-Chih Hsu Soenen, E. Roth, A. Gaither, J.
Copyright Year	2011
Description	Author affiliation: TSMC, 11921 N Mopac Expy, Austin, TX 78759, USA (Shi, J.; Ying-Chih Hsu; Soenen, E.; Roth, A.; Gaither, J.)
Abstract	This paper presents a digital DC-DC converter with $2^{nd}$ order compensation and direct battery connect capability in 40nm CMOS. A combination of circuit and process technology is used to achieve an input range up to 5.5V with peak efficiencies of 95%. It also outlines an approach to optimize a control loop based on a sigma-delta ADC and higher order digital filter, which is demonstrated on a prototype achieving step response times under load below 38µs/V.
Starting Page	1
Ending Page	4
File Size	519186
Page Count	4
File Format	PDF
ISBN	9781457702228
ISSN	08865930
e-ISBN	9781457702235
DOI	10.1109/CICC.2011.6055337
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital filters Regulators DC-DC power converters Logic gates Digital control IIR filters Batteries
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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