NDLI: A 4-GHz all digital fractional-N PLL with low-power TDC and big phase-error compensation

Content Provider	IEEE Xplore Digital Library
Author	Ja-Yol Lee Mi-Jeong Park Byonghoon Mhin Seong-Do Kim Moon-Yang Park Hyunku Yu
Copyright Year	2011
Description	Author affiliation: Electronics and Telecommunications Research Institute, USA (Ja-Yol Lee; Mi-Jeong Park; Byonghoon Mhin; Seong-Do Kim; Moon-Yang Park; Hyunku Yu)
Abstract	This paper presents an all-digital fractional-N PLL with a low-power TDC operating at the retimed reference clock. Two retimed reference clocks are employed to implement the proposed TDC estimating the fractional phase error between the reference clock and CKV clock. The application of the retimed reference clocks to TDC does not only reduce dynamic power in TDC delay inverter chain, but also simplify εr estimation including a new Tv calculation algorithm. Also, phase-error compensation block is presented to compensate for the big phase-error change due to timing skew in the output bits produced from variable-phase counter. And loop settling scanning block is invented to shift DCO operation mode and additionally decrease PLL channel switching time for frequency hopping applications. The proposed all-digital PLL represents − 36dBc integrated phase noise (1kHz – 20MHz), 778fs rms jitter, 9.6mW power consumption. The channel switching time of the ADPLL is measured as 630nsec.
Starting Page	1
Ending Page	4
File Size	555178
Page Count	4
File Format	PDF
ISBN	9781457702228
ISSN	08865930
e-ISBN	9781457702235
DOI	10.1109/CICC.2011.6055303
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Phase locked loops Phase noise TV Logic gates Timing Frequency measurement
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation

A 4-GHz low-power TDC-based all digital PLL having 9.6mW and 1.2ps rms jitter

A 1.9-GHz Fractional-N Digital PLL With Subexponent $ DeltaSigma$ TDC and IIR-Based Noise Cancellation

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With Delay-Cell-Less TDC

A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping $DeltaSigma$ TDC

A 2.8–3.2-GHz Fractional- $N$ Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO

A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation

digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture

A 4-GHz all digital fractional-N PLL with low-power TDC and big phase-error compensation

Similar Documents

A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation

A 4-GHz low-power TDC-based all digital PLL having 9.6mW and 1.2ps rms jitter

A 1.9-GHz Fractional-N Digital PLL With Subexponent $ DeltaSigma$ TDC and IIR-Based Noise Cancellation

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With Delay-Cell-Less TDC

A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping $DeltaSigma$ TDC

A 2.8–3.2-GHz Fractional- $N$ Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO

A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation

digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture

A 4-GHz all digital fractional-N PLL with low-power TDC and big phase-error compensation