NDLI: ReSSP: A 5.877 TOPS/W Reconfigurable Smart-camera Stream Processor

Content Provider	IEEE Xplore Digital Library
Author	Wei-Kai Chan Yu-Hsiang Tseng Pei-Kuei Tsung Tzu-Der Chuang Yi-Min Tsai Wei-Yin Chen Liang-Gee Chen Shao-Yi Chien
Copyright Year	2011
Description	Author affiliation: Media IC & System Lab. and DSP/IC Design Lab., Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan (Wei-Kai Chan; Yu-Hsiang Tseng; Pei-Kuei Tsung; Tzu-Der Chuang; Yi-Min Tsai; Wei-Yin Chen; Liang-Gee Chen; Shao-Yi Chien)
Abstract	A 5.877 TOPS/W Reconfigurable Smart-camera Stream Processor is implemented in 90nm CMOS technology. A reconfigurable hardware architecture with heterogeneous stream processing and subword-level parallelism is implemented to accelerate the vision processing for smart-camera applications. The area efficiency reaches 111.329 $GOPS/mm^{2}.$ The power efficiency and area efficiency are 4.5x to 33.0x and 3.8x to 74.2x better than the state-of-the-art works, respectively.
Starting Page	1
Ending Page	4
File Size	851781
Page Count	4
File Format	PDF
ISBN	9781457702228
ISSN	08865930
e-ISBN	9781457702235
DOI	10.1109/CICC.2011.6055296
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip Streaming media Hardware Memory management Throughput Silicon Logic gates
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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ReSSP: A 5.877 TOPS/W Reconfigurable Smart-camera Stream Processor