NDLI: A 50 MHz vision processor

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Strategies for CMOS/BiCMOS gate usage on sea-of-gates arrays

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Proceedings of the IEEE 1991 Custom Integrated Circuits Conference (Cat. No.91CH2994-2)

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A 50 MHz vision processor

Content Provider	IEEE Xplore Digital Library
Author	Sutardja, S. Fandrianto, J. Martin, B. Rainnie, H. Wang, C.-S.
Copyright Year	1991
Description	Author affiliation: Integrated Inf. Technol., Santa Clara, CA, USA (Sutardja, S.; Fandrianto, J.; Martin, B.; Rainnie, H.; Wang, C.-S.)
Abstract	A highly integrated microcoded motion video (de)compression digital signal processing chip that can perform 80010/sup 6/ 16-b multiply, shift, and accumulate operations, 80010/sup 6/ pixel absolute difference operations or 40010/sup 6/ 16-b addition-subtraction operations, and 80010/sup 6/ sum of difference operations in each second is described. The chip has been fabricated in a 1- mu m CMOS technology and has been tested to run at 50 MHz. When coupled with external interface circuitry, the vision processor is suitable for use in many consumer and desktop multimedia applications.<>
File Size	223898
File Format	PDF
ISBN	0780300157
DOI	10.1109/CICC.1991.164023
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-05-12
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Discrete cosine transforms Video compression Registers Motion estimation Teleconferencing Reduced instruction set computing Engines Random access memory Information technology Digital signal processing chips
Content Type	Text
Resource Type	Article

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