NDLI: A procedural datapath compiler for VLSI full custom applications

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Strategies for CMOS/BiCMOS gate usage on sea-of-gates arrays

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New state assignment algorithms for finite state machines using look ahead

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Reversible functional simulation for digital system design

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Performance and technology trade-offs of BiCMOS submicron processes for ASIC applications

A pipelined 9-stage video-rate analog-to-digital converter

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A procedural datapath compiler for VLSI full custom applications

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Timing driven routing and resistivity minimization

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An integrated design and characterization environment for the development of a standard cell library

Integrated-circuit reliability simulation including dynamic stress effects

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Automated generation of custom pad cells for ASICs

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Implementation of sub-10 ns serial access mode to a standard 64-Mb DRAM

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Proceedings of the IEEE 1991 Custom Integrated Circuits Conference (Cat. No.91CH2994-2)

IEEE Proceedings of the Custom Integrated Circuits Conference

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A procedural datapath compiler for VLSI full custom applications

Content Provider	IEEE Xplore Digital Library
Author	Taliercio, M. Foletto, G. Licciardi, L.
Copyright Year	1991
Description	Author affiliation: SGS Thomson Microelectron., Agrate Brianza, Italy (Taliercio, M.; Foletto, G.)
Abstract	A data path compiler mainly dedicated to VLSI full custom applications is described. It is dedicated both to the VLSI system designer, whose productivity will increase using macro blocks/generators and structured design, and to the VLSI CMOS full custom designer who, if necessary, could also add functions to the original library. The cells of this compiler have many interesting design solutions: the architecture is more efficient with respect to datapaths where leaf cells are very similar to standard cells, and the high number of tracks available covers almost all the designer's needs staying within 'over the cell routing' (this means no need to open an extra channel) and so with a larger density. Full integration with a complete standard CAD (computer-aided design) environment increases the whole design efficiency.<>
File Size	332789
File Format	PDF
ISBN	0780300157
DOI	10.1109/CICC.1991.163997
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-05-12
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Routing Libraries Integrated circuit interconnections Design optimization Timing Variable structure systems Automatic control MOS devices Current density
Content Type	Text
Resource Type	Article

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