NDLI: Design model for minority-carrier well-type guard-rings in CMOS circuits

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Strategies for CMOS/BiCMOS gate usage on sea-of-gates arrays

A silicon bipolar LSI chip set for 2.4 Gb/s fiber optic transmission

A 50-MHz 10-ns submicron BiCMOS 2-way set associative cache tag memory

New state assignment algorithms for finite state machines using look ahead

IC reliability simulation

A rail-to-rail video-band full Nyquist 8-bit A/D converter

Reversible functional simulation for digital system design

A quasi-complementary-logic GaAs gate array employing air-bridge metallization technology

Performance and technology trade-offs of BiCMOS submicron processes for ASIC applications

A pipelined 9-stage video-rate analog-to-digital converter

Pascant: a partial scan and test generation system

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A procedural datapath compiler for VLSI full custom applications

2-10 MHz programmable continuous-time 0.05 degrees equiripple linear phase filter

A photodetector array for a one terabyte optical tape recorder

A pragmatic approach to integrated process/device/circuit simulation for IC technology development

Static charge decay analysis of MOS circuits

A single-chip mixed analog/digital signal processor for voiceband applications

A single chip sensor and image processor for fingerprint verification

Submicron CBiCMOS technology with new well and buried layer formed by multiple energy ion implantation

A system for electromigration analysis in VLSI metal patterns

A Six Sigma program implementation

A system for synthesis of sequential machines with built-in testability

A SONET STS-3c user network interface IC

Symbolic verification of CMOS synchronous circuits using characteristic functions

A trainable analog neural chip for image compression

Test considerations for BiCMOS logic families

Timing driven routing and resistivity minimization

A transistor-only current-mode Sigma Delta modulator

10 Mb/s twisted pair CMOS transceiver with transmit waveform pre-equalization

Technology- and power-supply-independent cell library

The use of TCAD in semiconductor technology development

A tool towards integration of IC process, device, and circuit simulation

A 12-bit video BiCMOS track-and-hold amplifier using analog calibration

A vector digital signal processor LSI for speaker-independent voice pattern matching

A 50 MHz variable gain amplifier cell in 2 mu m CMOS

VLSI silicon based prosthesis for in vitro measurement of neural activity

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A sub-micron CMOS embedded SRAM compiler

SEAS: a simulated evolution approach for analog circuit synthesis

A 7 MHz 24-bit pipelined accumulator in 1.2- mu m CMOS for application as a numerically controlled oscillator

A 60 V-10 A intelligent power switch using standard cells

1.2 Gb/s integrated laser driver with temperature compensation for modulation current

Integrated digital modulator and analog front-end for GSM digital cellular mobile radio system

An integrated design and characterization environment for the development of a standard cell library

Integrated-circuit reliability simulation including dynamic stress effects

Improving DC convergence in a circuit simulator using a homotopy method

An integrated Si bipolar RF transceiver for a zero IF 900 MHz GSM digital mobile radio frontend of a hand portable phone

Improving BDDs manipulation through incremental reduction and enhanced heuristics

A high speed memory system based on 16 Mb ST (stretchable memory matrix) DRAMs

Hierarchical simulation of hot-carrier induced damages in VLSI circuits

A high speed BiCMOS table look-up gate

Hybrid routing on multichip modules

High performance self-checking adder for VLSI processor

A high performance digital processor for implementing large artificial neural networks

HECTOR: a hierarchical topology-construction program for analog circuits based on a declarative approach to circuit modeling

High-frequency characterization and modeling of polysilicon and diffusion lines

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Fast simulated diffusion: an optimization algorithm for multi-minimum problems and its application to MOSFET model parameter extraction

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Fully-differential CMOS current-mode circuits

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An efficient eigenvector-node interchange approach for finding netlist partitions

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An experimental approach to analog fault models

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Device sizing for silicon compilers using CSL

A direct sequence BPSK spread spectrum transceiver chip set

DYNAMO: a program for the simulation of transient faults in digital circuits

A dual-port SRAM compiler for 0.8- mu m 100 K BiCMOS gate arrays

The design of a monolithic, signal conditioned pressure sensor

Design model for minority-carrier well-type guard-rings in CMOS circuits

Digital logarithmic CMOS multiplier for very-high-speed signal processing

Device-level analysis of a 1 mu m BiCMOS inverter circuit operating at 77 K using a modified PISCES program

A data-flow processor for real-time low-level image processing

A 32 Mb/s disk drive data separator for constant density recording

DAVE: an automatic mixed analog/digital IC layout compiler

Dynamic asynchronous logic for high speed cMOS systems

A CMOS wideband amplifier with 800 MHz gain-bandwidth

Characterizing a VLSI standard cell library

A CMOS 4 ch*1 k time memory LSI with 1 ns resolution

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Calculation of total dynamic current of VLSI using a switch level timing simulator (RSIM-FX)

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Cell-shifting compaction of building-cell methodology for high-speed GaAs standard-cell LSIs

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A 170 MHz CMOS pixel processor for windowing graphics

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Current-mode logic techniques for CMOS mixed-mode ASICs

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A 5-V CMOS line controller with 16-bit audio converters

CMOS IC fault models, physical defect coverage, and I/sub DDQ/ testing

Circuit design for built-in current testing

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Current bias testing of differential circuits

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Calculation and application of time-domain waveform sensitivities in asymptotic waveform evaluation

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A bonded-SOI-wafer CMOS 16-bit 50-ksps delta-sigma ADC

A 3.3 V, 0.5 mu m BiCMOS technology for BiNMOS and ECL gates

A 1.9 ns BiCMOS CAM macro with double match line architecture

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A 0.8- mu m BiCMOS sea-of-gates implementation of the tandem banyan fast packet switch

3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules

A BiCMOS circuit family for a 0.45 mu m CMOS/BiCMOS sea of gates

An accurate MOS transistor model for submicron VLSI circuit-BSIMplus

ASIC technology applied to SONET multiplex, transmission, and cross-connect equipment

Analog statistical simulation

ACAP-a system for the interactive graphical capture of module generators

Accurate modeling and simulation of bridging faults

An analytical-model generator for interconnect capacitances

The architecture of the GenTest sequential test generator

Automated generation of custom pad cells for ASICs

On applying circular self-test path (CSTP) technique to circuits

Automatic custom layout of analog ICs using constraint-based module generation

Application of boundary-scan and full-chip BIST to a 3 ASIC chip set

An adaptive analog continuous-time CMOS biquadratic filter

Implementation of sub-10 ns serial access mode to a standard 64-Mb DRAM

CCD image sensor with differential, pyramidal output for lossless image compression

Can IDDQ test replace conventional stuck-fault test?

A knowledge based project plan generation and control system for ASIC design management

A 288-kbit fully parallel content addressable memory using stacked capacitor cell structure

New bit line architecture for ultra high speed SRAMs-T-shaped bit line and its real application to 256 k BiCMOS TTL SRAM

A large scale FPGA with 10 K core cells with CMOS 0.8 mu m 3-layered metal process

A new large signal model for heterojunction bipolar transistors including temperature effects

Modelling behaviour and tolerances in analogue cells

A 120 MFLOPS CMOS floating-point processor

Metastability of CMOS master/slave flip-flops

Memory chip for 24-port global register file

A modular flash EEPROM technology for 0.8 mu m high speed logic circuits

A 80 MFLOPS 64-bit microprocessor for parallel computer

A modular memory and process verification vehicle for a sub-micron BiCMOS telecom technology

Mixed mode simulation of slow transient effects in AlGaAs/GaAs HEMT inverters

A 1.5 MLIPS 40-bit AI processor

100 Mpixel/sec single-chip integrated graphics controller (IGC)

A multi-speed digital cross-connect switching VLSI using new circuit techniques in dual port RAMs

Memory synthesis for high speed DSP applications

A 10 bit 75 mega-sample per second A/D converter

A novel three dimensional BiCMOS process using epitaxial lateral overgrowth of silicon

Optimization of field-programmable gate array logic block architecture for speed

Optimal synthesis of high performance architectures

A CMOS 20 MHz 8 bit 50 mW ADC for mixed analog/digital ASICs

Proceedings of the IEEE 1991 Custom Integrated Circuits Conference (Cat. No.91CH2994-2)

IEEE Proceedings of the Custom Integrated Circuits Conference

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Proceedings of the IEEE 1988 Custom Integrated Circuits Conference

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