NDLI: A 8bit two stage time-to-digital converter using 16x cascaded time difference amplifier in 0.18um CMOS

Content Provider	IEEE Xplore Digital Library
Author	Mandai, S. Nakura, T. Ikeda, M. Asada, K.
Copyright Year	2010
Description	Author affiliation: Dept. of Electrical Engineering and Information Systems, The University of Tokyo, 2-11-16 Yayoi, Bunkyo-ku, 113-0032 Japan (Mandai, S.; Ikeda, M.; Asada, K.) \|\| VLSI Design and Education Center(VDEC), The University of Tokyo, 2-11-16 Yayoi, Bunkyo-ku, 113-0032 Japan (Nakura, T.)
Abstract	We have designed a 8bit two stage time-to-digital converter(TDC) using a time difference amplifier in 0.18um CMOS process. The time resolution is 1.89ps, and DNL of 0.9 and INL of 1.0 are achieved in simulation. To amplify the time residue of the first stage, the 16x cascaded time difference amplifier(TDA) using differential logic delay cells is employed. By using differential logic cells for the delay chain instead of CMOS logic cells, the 16x cascaded TDA realizes stable time difference gain(TD gain) and fine time resolution. The TDA have been fabricated in 0.18um CMOS process. Measurement results show that our TDA achieves 4.4% TD gain offset at 30ps input range, the standard deviation and the maximum error of the difference between the ideal amplified value and measured value is 13.0ps and 30.0ps respectively. The maximum error corresponds to 0.99 LSB. Linearity of the two stage TDC depends on the specifications of a TDA greatly. The linearity of the proposed TDC improved by using the 16x cascaded TDA and using only one TDA in the two stage TDC instead of using a lot of TDAs.
Starting Page	280
Ending Page	285
File Size	655323
Page Count	6
File Format	PDF
ISBN	9781424457939
e-ISBN	9781424457953
DOI	10.1109/MELCON.2010.5476285
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-26
Publisher Place	Malta
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS logic circuits Delay effects Signal resolution Linearity CMOS process Differential amplifiers Pulse amplifiers Gain measurement Space vector pulse width modulation Very large scale integration
Content Type	Text
Resource Type	Article

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