NDLI: Average power reduction in compression-based scan designs

Content Provider	IEEE Xplore Digital Library
Author	AlQuraishi, E. AlTeenan, R.
Copyright Year	2010
Description	Author affiliation: Computer Engineering Department, Kuwait University, Kuwait (AlQuraishi, E.; AlTeenan, R.)
Abstract	Toggling of scan cells during the shift of consecutive complementary values reflects into excessive switching activity in the combinational logic under test unnecessarily. Elevated levels of power dissipation during test ensue as a result, endangering the reliability of the chip. The test power problem may be alleviated via a proper specification of don't care bits to create transition-less runs of bit values. However, these don't care bits are rather reserved so as to ensure the encodability of patterns through the on-chip decompressor. In this paper, we propose a DfT-based approach for reducing test power in an Illinois scan architecture. The proposed on-chip mechanism enables the reconfigurable swapping of transition-wise costly stimulus fragments across different channels, absorbing these transitions and reducing power. The proposed solution reduces power without resorting to x-filling, enabling orthogonal x-filling techniques to be applied in conjunction. Experimental results justify the efficacy of the proposed swapping mechanism in attaining test power reductions.
Starting Page	504
Ending Page	509
File Size	180761
Page Count	6
File Format	PDF
ISBN	9781424457939
e-ISBN	9781424457953
DOI	10.1109/MELCON.2010.5476222
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-26
Publisher Place	Malta
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Power dissipation Logic testing Performance evaluation Clocks Broadcasting Power engineering computing Reliability engineering Design engineering Power engineering and energy
Content Type	Text
Resource Type	Article

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