NDLI: Reliability investigations of flip chip interconnects in FCOB and FCOG applications by FEA

Content Provider	IEEE Xplore Digital Library
Author	Schubert, A. Dudek, R. Doring, R. Michel, B.
Copyright Year	1998
Description	Author affiliation: Fraunhofer Inst. for Reliability & Microintegration, Berlin, Germany (Schubert, A.)
Abstract	One major concern over thermally induced mechanical stress is that it causes reliability problems in electronic device packaging and interconnects. IC packaging has accelerated development of flip chip structures as used in flip chip on board (FCOB) or flip chip on glass (FCOG) technology. Much testing is usually required to meet the reliability needs of an assembly or to optimize its design. Finite element analysis (FEA) is used to understand the reasons for failure and the critical parameters which may be varied; however, use of FEA generates difficulties concerning the geometrical description and constitutive modeling of the materials used. Solder joints, the most widely used FCOB interconnects, have relatively low structural compliance due to the large CTE mismatch between die and organic substrate. This causes high thermally induced creep strain on interconnects during temperature cycling and leads to early failure. Flip chip reliability can be enhanced by applying an epoxy-based underfill between chip and substrate. However, over ranges of design, process and material parameters, different failure modes are observed with significant dependence on material properties and geometry. Nonlinear FEA of flip chip structures is carried out to study the reliability impact of selected design and material parameters. Two fundamental issues are addressed: optimized manufacturing process-induced defects and underfill material thermo-mechanical properties. Anisotropic conductive films (ACF) are widely used for FCOG packaging. Nonlinear FEA simulations are conducted to investigate stress development and relaxation in ACF joints.
Starting Page	49
Ending Page	56
File Size	1591314
Page Count	8
File Format	PDF
ISBN	078035141X
DOI	10.1109/EPTC.1998.755978
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-12-10
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flip chip Conducting materials Electronic packaging thermal management Thermal stresses Integrated circuit packaging Acceleration Glass Testing Assembly Design optimization
Content Type	Text
Resource Type	Article

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