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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ng Hong Seng |
| Copyright Year | 2010 |
| Description | Author affiliation: X-FAB Sarawak Sdn. Bhd., 1 Silicon Drive, Sama Jaya Free Industrial Zone, 93350 Kuching, Sarawak, Malaysia (Ng Hong Seng) |
| Abstract | This paper suggests an improved method to round off the concave corners of the deep trenches formed by plasma etch. The corner rounding technique, sacrificial oxidation (SACOX) before gate oxidation, has been practiced on the shallow trench isolation (STI) to improve the CMOS leakage performance. However, the direct implementation of the SACOX on the deep trenched MOSFET having less than 0.5 um trench width is insufficient to eliminate the oxide thinning at the concave corners. The experimental results including the scanning electron microscopy (SEM) images are presented to illustrate how the sharp corners vanish. The concave corners are encompassed by a smooth layer of silicon dioxide served as a gate oxide for vertical trenched MOSFET. Electrical measurement shows that the breakdown voltage was improved by eliminating the gate oxide weak spots |
| Starting Page | 1 |
| Ending Page | 3 |
| File Size | 663768 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781424488254 |
| ISSN | 10898190 |
| e-ISBN | 9781424488278 |
| DOI | 10.1109/IEMT.2010.5746769 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-11-30 |
| Publisher Place | Malaysia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic gates Oxidation Silicon MOSFET circuits Stress Surface morphology Manufacturing |
| Content Type | Text |
| Resource Type | Article |
| Subject | Industrial and Manufacturing Engineering Electrical and Electronic Engineering |
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