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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chua, S.L. Razzaq, A. Wee, K.H. Li, K.H. Yu, H. Tan, C.S. |
| Copyright Year | 2014 |
| Description | Author affiliation: Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore (Chua, S.L.; Razzaq, A.; Li, K.H.; Yu, H.; Tan, C.S.) || DSO Nat. Labs., Singapore, Singapore (Wee, K.H.) |
| Abstract | 3D integration has been widely recognized as the next generation of technology for integrated microsystems with small form factor, high bandwidth, low power consumption, and possibility of heterogeneous More-than-Moore integration. Heterogeneous integration of MEMS and CMOS is critical in future development of multi-sensor data fusion in a low-cost chip size system. MEMS/CMOS integration was primarily done using monolithic and hybrid/package approaches until recently. In this work, 3D CMOS-on-MEMS stacking without TSV using direct (i.e. solder-less) metal bonding is demonstrated. This MEMS/CMOS integration leads to a simultaneous formation of electrical, mechanical, and hermetic bonds, eliminates chip-to-chip wire-bonding, and hence presents competitive advantages over hybrid or monolithic solutions. We present the fabrication flow and verify the performance of the stacked MEMS/CMOS microsystem in this paper. The micro-electro-mechanical system (MEMS) accelerometer is fabricated using bulk micromachining technology with silicon-on-insulator (SOI) substrate. The CMOS readout circuit for the capacitive MEMS accelerometer, implemented in 0.35 μm (2P4M) process, consists of three essential circuit blocks: (i) low noise, bandpass gain stage, (ii) synchronous demodulator and (iii) offchip, low-pass filter. The MEMS chip is metallized with a single layer of Au for electrical contact and sealing ring prior to bulk etching and release. Au is chosen to withstand harsh process conditions. The CMOS chip contains four Al metal layers. The top most layer is patterned for electrical contact and sealing ring that match those of the MEMS chip. In order to ensure proper operation, the delicate micro-structures (MEMS) should be protected from the ambient. In this approach, a hermetic seal ring is formed simultaneously during face-to-face stacking of CMOS on MEMS and hence eliminating the need for post-processing hermetic encapsulation. Face-to-face stacking also eliminates the need for chip-to-chip wire bonding. Effectively, the CMOS layer acts as an “active cap”. In addition, I/Os to the MEMS chip are routed through the CMOS metal layers to simplify the MEMS process. Since the I/O count is low, TSV is not used and electrical feed-through is achieved by peripheral pads. As no solder is applied, the top passivation layer of the CMOS chip is partially recessed to expose the CMOS metal layer for ease of direct bonding with the MEMS metal layer. The metal surfaces are carefully treated and bonded. The bonded samples are packaged inside 44-pin J-leaded ceramic package for testing. The functionality of the readout circuit is verified first, using off-chip MEMS, followed by verification of the bonded CMOS/MEMS chip. In both cases, the MEMS is excited by anti-phase sinusoid carriers within the frequency range 50 kHz-1 MHz. The variation in the peak-to-peak amplitude of the gain stage output is observed as the MEMS is flipped between -1 g/+1 g orientations. In addition, the phase of the output signal agrees with the flip direction. Testing for hermeticity of the Al-Au thermo-compression bond is done in accordance with the MIL-STD-883E standard. Passive sealed cavities with volume of about 1.4 × $10^{-3}$ $cm^{3}$ are fabricated and bonded at 300°C under a bonding pressure of around 8.4 MPa for 10 mins. The cavity chips are created by deep reactive ion etching (DRIE) on silicon followed by the deposition of 50 nm of Cr adhesion layer and 150 nm of Au with electron beam evaporation method. The blanket capping chips are deposited with 100 nm of $SiO_{2}$ by plasma-enhanced chemical vapor deposition (PECVD) and 150 nm of Al by sputtering. Bubble test is used for gross leak and helium test is used for fine leak inspection. For shear strength measurement, test samples are prepared using the same processes for the samples in hermetic test, without the creation of cavities. The bonding parameters are kept the same. Results from the hermeticty and shear tests are presented and discussed. |
| Starting Page | 324 |
| Ending Page | 331 |
| File Size | 2137313 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781479924073 |
| DOI | 10.1109/ECTC.2014.6897306 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-05-27 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Micromechanical devices Bonding CMOS integrated circuits Gold Cavity resonators Three-dimensional displays |
| Content Type | Text |
| Resource Type | Article |
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