NDLI: Trench transistor cell with self-aligned contact (TSAC) for megabit MOS DRAM

Content Provider	IEEE Xplore Digital Library
Author	Yanagisawa, M. Nakamura, K. Kikuchi, M.
Copyright Year	1986
Description	Author affiliation: NEC Corporation, Kanagawa, Japan (Yanagisawa, M.)
Abstract	A new one-transistor, one-capacitor MOS dynamic RAM cell structure called a Trench Transistor Cell with Self-Aligned Contact (TSAC) has been developed for 4M bit and beyond VLSI memory devices. Basic concept of the new cell structure is shrinkage of the conventional trench capacitor cell using the following technologies; (1) Trench transistor as a transfer gate, and (2) Bit line contact, which is self-aligned to the word line. Superior immunity of the trench transistor from short and narrow channel effects, combined with marginless contact design capability, enables substantial reduction of the memory cell size. Adopting submicron design rule, the new cell realizes extremely small cell size below 9 $µm^{2}.$ This enables reasonable size 4M bit chip, which can be encapsulated in a 300 mil DIP.
Starting Page	132
Ending Page	135
File Size	924080
Page Count	4
File Format	PDF
DOI	10.1109/IEDM.1986.191131
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1986-12-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Random access memory Fabrication Insulation DRAM chips Transistors Very large scale integration Capacitors Surface morphology Oxidation
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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