NDLI: Trench and compact structures for dRAMs

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Session 1 Plenary session — Invited papers

Modeling and simulation for VLSI

"Submicron bipolar technology - new chances for high speed applications"

Flat-panel displays

Session 2 Modeling and simulation — Bipolar transport and circuit modeling

Minority carrier transport in silicon

Measurement of electron lifetime, electron mobility and band-gap narrowing in heavily doped p-type silicon

Majority and minority carrier transport in polysilicon emitter contacts

A thermionic-diffusion model of polysilicon emitter

Numerical techniques lead to exact solution of berkeley bipolar model

A measurement-based charge sheet capacitance model of short-channel MOSFET's for SPICE

Session 3 Device technology — Advanced interconnect and contact technologies

Perfect hillockless metallization (PHM) process for VLSI

Selective tungsten on aluminum for improved VLSI interconnects

Al tapered etching application to submicron multilevel interconnection process

Mechanisms for process-induced leakage in shallow silicided junctions

Thermally stable W/Silicide/Si contact

Selective CVD tungsten via plugs for multilevel metallization

The flowage bias sputter method for planarized aluminum interconnections in VLSIs

Session 4 Quantum electronics and compound-semiconductor devices — Novel heterostructure devices

A novel quantum interference transistor (QUIT) with extremely low power-delay product and very high transconductance

Determination of elastic tunneling traversal times

The MBE grown GaAs quantum well base hot electron transistors

Study of heterostructure launchers for generation of ballistic electrons

Theory and experiment of heterojunction bipolar transistor at very low temperatures

A 3.3-ps Josephson or gate with Niobium junctions

Electronic and optoelectronic characterization of Au Schottky barrier contacts on MOCVD grown (1) GaAs/Ge, (2) GaAs/Ge/Si and (3) GaAs/Si

Session 5 Solid-state devices — Discrete power devices

Revolutionary innovations in power discrete devices

Turn-off dynamics of a new very fast switching 1000 V, 50 A bipolar power transistor

Properties of a high-power field-controlled thyristor

Gate turn-off thyristors with near perfect technology

Effect of temperature and load on MCT turn-off capability

1800V bipolar-mode MOSFETs: A first application of silicon wafer direct bonding (SDB) technique to a power device

Session 6 Integrated circuits — Dynamic memory concepts and techniques

Trench and compact structures for dRAMs

Trench transistor cell with self-aligned contact (TSAC) for megabit MOS DRAM

Dielectrically encapsulated trench capacitor cell

Trench capacitor design issues in VLSI DRAM cells

A high density 4M DRAM process using folded bitline adaptive side-wall isolated capacitor (FASIC) cell

Triple layered SOI dynamic memory

Session 7 Electron tubes — TWTs and klystrons

Status and prospects for microwave tubes

Scaling laws and power limits for klystrons

A UHF-TV klystron using multistage depressed collector technology

Non-brazed helix TWT attained 3kW output at C-band and 600W at KU-band

High-power, high efficiency wideband TWTs

Session 8 Detectors, sensors and displays — Microsensor fabrication technology

Fabrication techniques for integrated sensor microstructures

Microfabrication technology for development of chronic neural information transducers

Micro-diaphragm pressure sensor

Sensitivity of the silicon high-resolution 3-dimensional magnetic-field vector sensor

Amorphous Si electronic devices and their applications

Sub-µm polysilicon super thin film transistor

The hetrojunction amorphous $n^{+}(a-Si)/n-i-p(a-SiC)/i-n^{+}(a-Si)$ phototransistor with high gain (∼40) and high speed (∼10µs)

Properties of silicon oxide films grown in a microwave oxygen plasma

Improved dielectrically isolated device integration by silicon-wafer direct bonding(SDB) technique

A novel isolation structure for SMARTpower ICs

Fast switching lateral insulated gate transistor

Analysis and characterization of the hybrid Schottky injection field effect transistor

High voltage complementary gated MOS thyristors

Advanced 1200v HVIC technology

Session 10 Integrated circuits — CMOS technology

0.5µm-channel CMOS technology optimized for liquid-nitrogen-temperature operation

High speed CMOS technology for ASIC application

A versatile, high-performance, double-level-poly double-level-metal, 1.2-micron CMOS technology

Three-dimensional effects in CMOS latch-up

A symmetric submicron CMOS technology

A high performance submicron CMOS process with self-aligned chan-stop and punch-through implants (Twin-Tub V)

Session 11 Quantum electronics and compound-semiconductor devices — Heterojunction bipolar transistors

GaAlAs/GaAs heterostructure bipolar transistors: Experiment and theory

High-speed AlGaAs/GaAs HBTs with proton-implanted buried layers

Fabrication and modeling of a novel self-Aligned AlGaAs/GaAs heterojunction bipolar transistor with a cutoff frequency of 45 GHz

High-temperature stable W5Si3/In0.53Ga0.47As ohmic contacts to GaAs for self-aligned HBTs

Base doping effects in InGaAs/InP double heterostructure bipolar transistors

Quantum well resonant tunneling bipolar transistor operating at room temperature

A resonant-tunneling bipolar transistor (RBT): A proposal and demonstration for new functional devices with high current gains

Session 12 Device technology — Advanced fabrication technology

The effects of weak gate-to-drain(source) overlap on MOSFET characteristics

A novel scaled down oxygen implanted polysilicon resistor for future static RAMs

1.0 µm CMOS process for highly stable tera-ohm polysilicon load 1Mb SRAM

Characterization of IC devices fabricated in low temperature (550°c) epitaxy by UHV/CVD technique

LECR RIBE for submicron patterning

Excimer laser-based lithography for 0.5 µm device technology

Half-micron photolithography using a KrF excimer laser stepper

Session 13 Electron tubes — Fast wave tubes

Intense microwave generation with a free-electron laser amplifier

Design and operation of a 200 kW CW, 140 GHz gyrotron oscillator

Initial operation of a 1 MW, 140 GHz gyrotron

Experimental design of a 30 MW, 10 GHz gyroklystron

Frequency and phase synchronization of a gyromonotron using a modulated electron beam

Initial tests of the NRL ubitron

A high harmonic gyro-TWTA

Session 14 Detectors, sensors and displays — Image sensors

Quantum efficiency model for the CCD flash gate

A new MOS image sensor operating in a non-destructive readout mode

A 640 Megapixel/sec 512 × 512 interline transfer virtual phase CCD

Three-dimensional integrated sensors

New technologies in dual channel read-out registers for high-density CCD image sensor

Smear-less SOI image sensor

Three-dimensional analytical model for photovoltaic detector arrays

Session 15 Solid-state devices — Scaling issues for device operation

Low temperature CMOS devices and technology

Reliability in submicron MOSFETs stressed at 77 K

Mechanical stress and hydrogen effects on hot carrier injection

Lifetimes and substrate currents in static and dynamic hot-carrier degradation

Degradation of very thin gate oxide MOS devices under dynamic high field/Current stress

Power supply voltage for future CMOS VLSI in half and sub micrometer

Complementary silicon MESFETs for VLSI

Session 16 Device technology — Bipolar and SOI technologies

Advanced BiCMOS technology for high speed VLSI

On the impurity profiles of down scaled bipolar transistors

A 3GHz lateral PNP transistor

A high-speed bipolar LSI process using self-aligned double diffusion polysilicon technology

Submicron epitaxial layer and RTA technology for extremely high speed bipolar transistors

The current status of silicon-on-insulator technologies - a comparison

The "ISLANDS" method—A manufacturable porous silicon SOI technology

Fabrication technologies for dual 4-kbit stacked SRAM

Session 17 Quantum electronics and compound-semiconductor devices — III-V heterostructure FET devices

The application of OMCVD to high performance two-dimensional electron gas structures

Self-aligned processes for the GaAs gate FET

Complementary heterostructure insulated gate FET circuits for high-speed, low power VLSI

Development of a one transistor dynamic RAM for the AlGaAs/GaAs HIGFET technology

III-V heterojunction field effect transistor using indium alloys

New pseudomorphic MODFETs utilizing Ga0.47-uIn0.53+uAs/Al0.48+uIn0.52-uAs heterostructures

Power and noise performance of the pseudomorphic modulation doped field effect transistor at 60 GHz

Session 18 Integrated circuits — Advanced circuit technologies

Technology improvement for high speed ECL RAMs

63 ps ECL circuits using advanced SICOS technology

Ultrahigh-speed GaAs static frequency dividers

Advances in packaging for VLSI systems

Electrostatic discharge protection for one micron CMOS devices and circuits

Concept and basic technologies for 3-D IC structure

Session 19 Electron tubes — MM wave devices

A ladder circuit coupled-cavity TWT at 80-100 GHz

Heat transfer and power capabilities of EHF helix TWT's

44 GHz helix TWTs for satellite communication systems

Brazed-helix technology for 30 GHz power TWTs

Control of phase and gain deviations in an octave bandwidth EHF TWT

Spectral characteristics of the orotron

A high power coaxial TWT for wide-band millimeter wave amplification

Session 20 Modeling and simulation — Process and soft-errors

New n-well fabrication techniques based on 2D process simulation

Process physics determining 2-D impurity profiles in VLSI devices

Simulation of stress effects on reaction kinetics and oxidant diffusion in silicon oxidation

Thermoelastic model of dislocations in wafers

Modeling dopant redistribution in SiO2/WSi2/Si structure

Single event charge collection modeling in CMOS multi-junctions structure

The scaling law of alpha-particle induced soft errors for VLSI's

Session 21 Power semiconductor devices: Status and trends

Session 22 Roadblocks to progress in VLSI

Session 23 Flat panel displays

Session 24 Device modeling beyond drift-plus-diffusion transport

Session 25 Modeling and simulation — Advanced devices

Scaling and transport properties of high electron mobility transistors

Monte-Carlo modeling of hot electron gate current in MOSFETs

Multi-window device analysis of hot carrier transport

Self-consistent calculation of electron states in narrow channels

Quantum transport simulation of the resonant-tunneling diode

A two-dimensional numerical model of amorphous silicon thin-film transistors

Session 26 Integrated circuits — Nonvolatile and static memory technology

Comparison and trends in today's dominant $E^{2}technologies$

A novel high-speed, 5-volt programming EPROM structure with source-side injection

Three transistor cell for high speed CMOS EPROM technology

High density contactless, self aligned EPROM cell array technology

A selectively pumped p-well memory array technology for high density static RAMs

A high-performance CMOS technology for very fast static RAMs

Session 27 Quantum electronics and compound-semiconductor devices — Semiconductor lasers and photodetectors

Laser devices for coherent optical communication

High switching-speed optical RS flip-flop constructed of a TM-wave injected semiconductor laser

Near single carrier-type multiplication in a multiple graded-well structure for a solid-state photomultiplier

A single-step MOCVD technology for AlGaAs BH lasers

Monolithic two-dimensional GaInAsP/InP laser arrays

Mixed-mode phase-locked quantum well laser arrays

Low threshold visible electron-beam-pumped-lasers

Session 28 Solid-state devices — Advanced FETs and device reliability

VDMOS Transistors with improved on-resistance and quasi-saturation characteristics

Deep-trench power MOSFET with an Ron Area product of 160 $mΩ.mm^{2}$

Ultra low specific on-resistance UMOS FET

The effects of SIPOS passivation on DC and switching performance of high voltage MOS transistors

Reliability analysis of self-aligned bipolar transistor under forward active current stress

Carrier multiplication in self-aligned bipolar transistors - applications in process monitoring and failure analysis

Session 29 Device technology — Thin dielectrics

Oxide breakdown dependence on thickness and hole current - enhanced reliability of ultra thin oxides

Dynamic stressing of thin oxides

MOS Electrical characteristics of low pressure re-oxidized nitrided-oxide

Imaging and detection of current conduction in dielectric films by emission microscopy

Application of rapid thermal oxidation to the development of high dielectric strength polyoxides

Electrical properties of thin Ta2O5films grown by chemical vapor deposition

Oxidized Ta2O5/Si3N4dielectric films for ultimate-STC dRAMs

Session 30 Electron tubes — Reliability, cathodes and optics

TWT Reliablity in space

Clad periodic permanent magnet structures for electron-beam guidance

Raman scattering as a diagnostic technique for cathode characterization

Emission degradation characteristics of coated dispenser cathodes

Coverage and work function of dispenser cathodes

Diagnostic techniques with a computer controlled beam analyzer

A computerized three dimensional approach to beam measurement and analysis

Session 31 Solid-state devices — Hot carrier effects

Impact of hot electron trapping on half micron PMOSFETs with $p^{+}poly$ Si gate

Investigation and reduction of hot electron induced punchthrough (HEIP) effect in submicron PMOSFETs

New degradation phenomena by source and drain hot-carriers in half-micron P-MOSFETs

Parasitic resistance characterization for optimum design of half micron MOSFETs

Mechanism of hot carrier induced degradation in MOSFET's

Modeling of hot electron effects on the device parameters for circuit simulation

A novel submicron LDD transistor with inverse-T gate structure

Session 32 Quantum electronics and compound-semiconductor devices — High speed III-V MESFETs/MISFETs

Performance of digital GaAs E/D MESFET circuits fabricated in GaAs-on-Si substrate

Microwave characterization of quarter-micron GaAs metal semiconductor field effect transistors on Si substrates

GaAs-MESFETs fabricated in SOI layers on crystalline CaxSr1-xF2insulator films

A 760mS/mm $N^{+}self-aligned$ enhancement mode doped-channel MIS-like FET (DMT)

High performance LDD GaAs MESFETs with SiF2+ -implanted extremely shallow channels

High-power high-efficiency stable indium phosphide MISFETs

Microwave AlxGa1-xAs hetero-MIS gate depletion-mode InP field effect transistors

Session 33 Electron tubes — New technology and analysis

A vacuum field effect transistor using silicon field emitter arrays

Ultra small electron beam amplifiers

Compact multibeam klystron

A Cherenkov cyclotron autoresonance maser

Control of emittance growth in PPM focussed TWT's

Holistic design strategy for GaAs advanced signal processors

Signal processor architectures and implementations based upon gallium arsenide digital integrated circuits: The need for a wholistic design approach

Bipolar CMOS merged structure for high speed M bit DRAM

Design features and initial test results of an 8 GHz gyrotron oscillator

Micromachined ZnO on silicon nitride pressure sensor

Self-aligned AlGaAs/GaAs heterojunction bipolar transistors for high-speed digital circuits

A planar multi-level tungsten interconnect technology

New SOI CMOS process with selective oxidation

A new heterostructure FET

High frequency modulation doped field effect transistors in InAlAs/InGaAs/InP material system

Electron velocity overshoot at 300 K and 77 K in silicon MOSFETs with submicron channel lengths

New ultra-high density textured Poly-Si floating gate EEPROM cell

MBE Grown GaAs MESFETs with ultra-high gmand fT

High-performance GaAs MESFET's

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Trench and compact structures for dRAMs

Content Provider	IEEE Xplore Digital Library
Author	Chatterjee, P.
Copyright Year	1986
Description	Author affiliation: Texas Instruments, Inc., Dallas, Texas (Chatterjee, P.)
Abstract	There have been a large variety of trench based dRAM cells proposed in the last few years. This paper attempts to establish the requirements of a 4Megabit cell and classify the various trench based approaches. The original trench capacitor and its limitations are described and three classes of trench capacitors that attempt to overcome these limits are described. The first is the inside out capacitor where the roles of the storage electrode and the cell plate are interchanged. In the second class the trench serves to isolate as well as increase the available storage area. The third type builds a two concentric plates inside the trench. These can be attached to a planer transistor or a trench transistor to form a large number of combinations. These concepts are graded according to probability of success.
Starting Page	128
Ending Page	131
File Size	482947
Page Count	4
File Format	PDF
DOI	10.1109/IEDM.1986.191130
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1986-12-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitors Dielectrics Electric breakdown Metalworking machines Doping Protection Testing Etching Costs Production
Content Type	Text
Resource Type	Article

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