NDLI: Large-signal transient behavior of metal-oxide-semiconductor transistors (MOST)

Content Provider	IEEE Xplore Digital Library
Author	Capocaccia, F.E. Pregnana, M. Vignola, G.
Copyright Year	1965
Description	Author affiliation: Olivette-General Electric (Capocaccia, F.E.)
Abstract	The plane of the drain characteristics of the MOST is divided into three regions: cut-off. (I), conduction beyond (II) and below (III) pinch-off. The large-signal operation of the device is represented by a non-linear equivalent circuit, derived from C. T. Sah's small-signal equivalent circuit, where the current source is modified in order to describe the drain characteristics of the device in the three regions. A basic inverter circuit is used for switching analysis. The amplitude of the voltage step applied to the input is sufficient to drive the MOST from region I to II or III and vice versa. Both the turn-on and turn-off times are expressed as sums of two terms: a delay and a switching time. The delay is due to the gate to drain capacitance which causes a fraction of the input step to appear at the output: the delay is defined as the time required for the output voltage to recover its initial value. The switching times are defined at the 90% at the output voltage excursion. While the turn-off transient lends itself to a very simple analysis, the turn-on transient may consist of two parts (in case region III is reached): a constant current transient (region II) followed by a transient (region III) where a square-law current -- voltage relationship applies. The analysis leads to rather complex formulae: a normalized diagram is supplied for quick calculations. Experimental results are shown. Finally the intrinsic parameters and the external variables affecting the switching behavior of the device are summarized.
Starting Page	63
Ending Page	63
File Size	92814
Page Count	1
File Format	PDF
DOI	10.1109/IEDM.1965.187630
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1965-10-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage Transient analysis Delay effects Silicon Conductivity Capacitance Aircraft Germanium Charge carrier processes Diodes
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A silicon, planar space-charge-limited current triode

Part V - The Properties of Metal to Semiconductor Contacts

Large-signal transient effect in avalanche diodes

Compact modeling for SiGe HBTs

Low-voltage SiGe power diodes

Lattice-Mismatch and CMOS

A fast, high-gain silicon photodiode

Design of Si/SiGe heterojunction complementary metal-oxide-semiconductor transistors

Using thin emitters to control BVce0 effects in punch-through diodes for ESD protection

Large-signal transient behavior of metal-oxide-semiconductor transistors (MOST)

Similar Documents

A silicon, planar space-charge-limited current triode

Part V - The Properties of Metal to Semiconductor Contacts

Large-signal transient effect in avalanche diodes

Compact modeling for SiGe HBTs

Low-voltage SiGe power diodes

Lattice-Mismatch and CMOS

A fast, high-gain silicon photodiode

Design of Si/SiGe heterojunction complementary metal-oxide-semiconductor transistors

Using thin emitters to control BVce0 effects in punch-through diodes for ESD protection

Large-signal transient behavior of metal-oxide-semiconductor transistors (MOST)