NDLI: Distributed model for high-frequency bi-polar transistors

Content Provider	IEEE Xplore Digital Library
Author	Dhaka, V.A.
Copyright Year	1965
Description	Author affiliation: IBM, East Fishkill, N. Y. (Dhaka, V.A.)
Abstract	A distributed model of a transistor which takes into account the lateral voltage drop across the emitter width is described. The distributed equivalent is obtained by dividing the active transistor into small sections, each of which is then represented by a π-equivalent lumped transistor. Other phenomena incorporated in this model are: 1. Base stretching into the collector region at high current densities 2. Conductivity modulation in the base region 3. Storage of mobile carriers in the depletion regions 4. Base width modulation because of collector base bias 5. Voltage dependence of junction capacitances 6. Injection dependence of semiconductor parameters 7. Surface effects A computer program which solves for transient, dc, and ac response for the above transistor model in common-emitter configuration is also presented. The inputs for this program (besides external circuit parameters) are: 1. Transistor horizontal geometry 2. Transistor impurity profile 3. Semiconductor parameters This program was used to design and fabricate a silicon transistor with Ft1.8 gHzat VCB= 0. Effect of variations in horizontal geometry and impurity profile on switching speeds are quantitatively shown and are compared with present state-of-the-art transistors. Additionally, this Program will enable us to custom-design transistors, to pin-point the most promising area of transistor research, and, finally, to indicate the ultimate limit (speed) of silicon transistors.
Starting Page	23
Ending Page	23
File Size	89860
Page Count	1
File Format	PDF
DOI	10.1109/IEDM.1965.187536
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1965-10-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage Geometry Semiconductor impurities Silicon Current density Conductivity Region 3 Region 4 Capacitance Circuits
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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