NDLI: Sixteen bit monolithic memory array clip

Content Provider	IEEE Xplore Digital Library
Author	Agusta, B. Bardell, P. Castrucci, P.
Copyright Year	1965
Description	Author affiliation: IBM, Hopewell Junction, N. Y. (Agusta, B.)
Abstract	A 70 × 70 mil monolithic silicon memory chip has been successfully fabricated which is used as a unit building block to structure a three dimensional high speed scratch pad memory. The chip contains 16 memory cells with each cell consisting of 5 transistors and 4 resistors. The memory array can be non-destructively read with an 8 nanosecond pulse width and requires a 20 nanosecond write pulse width. The "one" signal level is 60 millivolts into a 20 ohm sense load with essentially an infinite signal to noise ratio. The integrated silicon devices have npn planar diffused structures with junction isolation. The circuits have single level fixed pattern interconnections on thermally grown oxide with one underpass resistor per cell to provide the crossing of signal lines.
Starting Page	39
Ending Page	39
File Size	91509
Page Count	1
File Format	PDF
DOI	10.1109/IEDM.1965.187575
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1965-10-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Signal to noise ratio Plasma temperature Space vector pulse width modulation Resistors Germanium Wavelength measurement Silicon devices Circuits Thermal resistance Telephony
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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