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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wakabayashi, H. Ezaki, T. Hane, M. Yamagami, S. Ikarashi, N. Takeuchi, K. Yamamoto, T. Mogami, T. Ikezawa, T. Sakamoto, T. Kawaura, H. |
| Copyright Year | 2002 |
| Description | Author affiliation: Silicon Syst. Res. Labs., NEC Corp., Kanagawa, Japan (Wakabayashi, H.; Ezaki, T.; Hane, M.; Yamagami, S.; Ikarashi, N.; Takeuchi, K.; Yamamoto, T.; Mogami, T.) |
| Abstract | Transport properties of sub-10-nm planar bulk MOSFETs have been evaluated. Direct-tunneling currents between source and drain (S/D) regions with not only the gate-length effects but also "drain-induced tunneling modulation (DITM)" effects are clearly observed for sub-10-nm CMOS devices at low temperature. Moreover, a quantum mechanical (QM) simulation reveals that the tunneling currents increase with the increase in the temperatures and gate voltages, resulting in the significant contribution to the subthreshold current even at 300 K. Therefore, it is strongly required that the supply-voltage should be reduced, to suppress the DITM effects for the sub-10-nm CMOS devices even under the room-temperature operations. |
| Starting Page | 429 |
| Ending Page | 432 |
| File Size | 307498 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780386841 |
| DOI | 10.1109/IEDM.2004.1419178 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-12-13 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | MOSFETs Tunneling Temperature Laboratories Voltage control Threshold voltage Subthreshold current Silicon National electric code CMOS technology |
| Content Type | Text |
| Resource Type | Article |
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