NDLI: Reduction of Substrate Noise in Sub Clock Frequency Range

Content Provider	IEEE Xplore Digital Library
Author	Sherazi, S. Asif, S. Backenius, E. Vesterbacka, M.
Copyright Year	2004
Abstract	We propose a method of reducing the switching noise in the substrate of an integrated circuit. The main idea is to design the digital circuits to obtain a periodic supply current with the same period as the clock. This property locates the frequency components of the switching noise above the clock frequency. Differential return-to-zero signaling is used to reduce the data-dependency of the current. Circuits are implemented in symmetrical precharged DCVS logic with internally asynchronous D registers. A chip was fabricated in a standard 130-nm CMOS technology holding two versions of a pipelined 16-bit adder. First version employed the proposed method, and second version used conventional static CMOS logic circuits and TSPC registers. The respective device counts are 1190 and 684, and maximal operating frequencies 450 and 375 MHz. Frequency domain measurements were performed at the substrate node with on-chip generated sinusoidal and pseudo-random data at a clock frequency of 300 MHz. The sinusoidal case resulted in the largest frequency components, where an 8.5 dB/Hz decrease in maximal power is measured for the proposed circuitry at a cost of three times larger power consumption.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	1287
Ending Page	1297
Page Count	11
File Size	2977887
File Format	PDF
ISSN	15498328
Volume Number	57
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Noise reduction Clocks Integrated circuit noise CMOS logic circuits Registers CMOS technology Frequency measurement Switching circuits Digital circuits Current supplies substrate noise Flip-flops integrated circuit noise mixed analogdigital integrated circuits simultaneous switching noise
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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