NDLI: A study of reduced-terminal models for system-level SSO noise analysis

Content Provider	IEEE Xplore Digital Library
Author	Myunghyun Ha Joong-Ho Kim Dan Oh Swaminathan, M.
Copyright Year	2010
Description	Author affiliation: Rambus Inc., 4440 El Camino Real, Los Altos, CA 94022, USA (Joong-Ho Kim; Dan Oh) \|\| Georgia Institute of Technology, 85 5th St NW, Atlanta 30308, USA (Myunghyun Ha; Swaminathan, M.)
Abstract	SSO noise modeling imposes significant challenges in signal integrity analysis as it requires a complex model which represents numerous signal, power, and ground conductors and planes. Even with effective macros modeling techniques, the resulting model is still complex due to a large number of external nodes which often represent data, power, and ground pins or pads. This paper discusses several options to reduce the number of external nodes for SSO simulation. Both signal and power nodes are reduced based on the worst case aggressor switching activities. Significance of placing supernode in reduction of signal nodes is discussed. Low power memory system is considered as a numerical example to demonstrate and compare the accuracy of each option.
Starting Page	49
Ending Page	52
File Size	556780
Page Count	4
File Format	PDF
ISBN	9781424468652
e-ISBN	9781424468676
e-ISBN	9781424468669
DOI	10.1109/EPEPS.2010.5642541
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Noise Complexity theory Solid modeling Silicon Integrated circuit modeling Data models Driver circuits model reduction signal intergrity power integrity SSO analysis worst case analysis
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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