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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ikemiya, K. Kanazawa, M. Sudo, T. Masuda, S. Hirakawa, Y. Wada, K. |
| Copyright Year | 2012 |
| Description | Author affiliation: Shibaura-Institute of Technology, 3-7-5 Toyosu, Koto-ku Tokyo, Japan (Ikemiya, K.; Kanazawa, M.; Sudo, T.) || NEC AccessTechnica Co., Ltd, 800 Shimomata, Kakegawa Shizuoka, Japan (Masuda, S.; Hirakawa, Y.; Wada, K.) |
| Abstract | Three dimensionally stacked package using FFCSP (Flexible carrier Folded real Chip Size Package) has been developed as one solution of high-density DRAM module. FPC (Flexible printed circuit) was effectively utilized to construct the pads at the both top and bottom sides of PoP (package-on-package) structure. In such multi-tiered package structures, the power supply stability for the upper tiered package is estimated to be worse than that of the lower tiered package due to parasitic inductance. In this paper, the co-analysis model including signal integrity (SI) and power integrity (PI) has been established to evaluate the power supply and signal quality among the multi-tiered chips. In particular, the power distribution networks (PDN) and eye diagrams for multi-tiered package were discussed. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 2732347 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467307185 |
| ISSN | 23250364 |
| e-ISBN | 9781467307178 |
| DOI | 10.1109/EMCEurope.2012.6396881 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-09-17 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Solid modeling Power supplies Noise DRAM chips Impedance Integrated circuit modeling |
| Content Type | Text |
| Resource Type | Article |
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