NDLI: RC passive equalizer for through silicon via

Content Provider	IEEE Xplore Digital Library
Author	Ruey-Bo Sun Chang-Yi Wen Ruey-Beei Wu
Copyright Year	2010
Description	Author affiliation: Department of Electrical Engineering and Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan (Ruey-Bo Sun; Chang-Yi Wen; Ruey-Beei Wu)
Abstract	A resistance and capacitance (RC) passive equalizer is proposed to improve the eye diagram of a through silicon via (TSV) in this paper. To begin with, an analytical circuit model of the TSV is derived by using the transmission line theory, and based on which, the simplified circuit model is obtained. It is shown that the insertion loss of the TSV from DC to several GHz mainly depends on the capacitance of the oxide film and the lossy silicon substrate. Due to this inherent property of the TSV, the proposed RC equalizer can be designed to perfectly compensate these two lossy effects. Besides, the design formula is also given. A ten-stacked TSV with a PRBS of 20 Gb/s bit rate and 20 ps rising edge is taken as an example. By the help of the RC equalizer, the output eye diagram has nearly zero timing jitter and two times improvement in eye opening.
Starting Page	45
Ending Page	48
File Size	601019
Page Count	4
File Format	PDF
ISBN	9781424468652
e-ISBN	9781424468676
e-ISBN	9781424468669
DOI	10.1109/EPEPS.2010.5642540
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Through-silicon vias Integrated circuit modeling Silicon Equalizers Capacitance Substrates Insertion loss through silicon via (TSV) Equalizer
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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