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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wu, L. Li, C. |
| Copyright Year | 2006 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Memorial Univ. of Newfoundland, St. John's, Nfld. (Wu, L.; Li, C.) |
| Abstract | New generation routers and switches have large amount of ports with each link operates at multiple Gbps. The equipped buffers for queues are usually huge for each router and switch. How to improve the buffer efficiency and minimize the required buffer size are great concerns for the design and implementation of packet switches. In this paper, we propose a dynamic reconfigurable buffer sharing scheme for an ideal non-blocking output queued packet switch based on SRAM-DRAM architecture. The SRAMs serve as interfaces between central memory and input/output links and will provide higher operation speed. The large main storage will be in DRAM. Using the scheme we proposed, buffer space to each port can be allocated dynamically according to their traffic load and queue status at runtime |
| Starting Page | 1359 |
| Ending Page | 1362 |
| File Size | 201248 |
| Page Count | 4 |
| File Format | |
| ISBN | 1424400384 |
| DOI | 10.1109/CCECE.2006.277609 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-05-07 |
| Publisher Place | Canada |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Performance analysis Queueing analysis Switches Space technology Packet switching Random access memory Buffer storage High performance computing Electronic mail Computer architecture reconfigurable architecture Buffer sharing broadband packet switch output queuing |
| Content Type | Text |
| Resource Type | Article |
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