NDLI: QOS Driven Network-on-Chip Design for Real Time Systems

Content Provider	IEEE Xplore Digital Library
Author	Agarwal, Ankur Mustafa, M. Pandya, A.S.
Copyright Year	2006
Description	Author affiliation: Dept. of Comput. Sci. Eng., Florida Atlantic Univ., Boca Raton, FL (Ankur Agarwal)
Abstract	Real time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogeneous multiprocessor architecture platform. Such a multiprocessor system on chip (MPSoC) platform has set new innovative trends for the real-time systems and system on chip (SoC) designers. The consequences of this trend imply the shift in concern from computation and sequential algorithms to modeling concurrency, synchronization and communication in every aspect of hardware and software co-design and development. These problems have been addressed by the use of packet switched network on chip (NOC) architecture for future SoCs and thus, real-time systems. Such a NOC based system should be able to support different levels of quality of service (QoS) to meet the real time systems requirements. Thus, it becomes extremely critical to properly design a network interface (NT) and the communication backbone for NOC. In this paper we present a component based design of network interface and communication backbone which supports different levels of QoS. The design has been tested for an adaptive wormhole routing with proactive turn prohibition to guarantee deadlock free on chip communication for NOC architecture. In this work we propose to use the modified turn prohibition (MTP), which has been shown to perform better than up/down and the turn prohibition
Starting Page	1291
Ending Page	1295
File Size	300542
Page Count	5
File Format	PDF
ISBN	1424400384
DOI	10.1109/CCECE.2006.277852
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-07
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Network-on-a-chip Real time systems Quality of service Computer architecture System-on-a-chip Network interfaces Spine Embedded system Multiprocessing systems Software algorithms real-time-systems Network-on-chip network interface quality-of-service
Content Type	Text
Resource Type	Article

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