NDLI: An FPGA-Based Singular Value Decomposition Processor

Content Provider	IEEE Xplore Digital Library
Author	Weiwei Ma Kaye, M.E. Luke, D.M. Doraiswami, R.
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. & Comput. Eng., New Brunswick Univ., Fredericton, NB (Weiwei Ma; Kaye, M.E.; Luke, D.M.; Doraiswami, R.)
Abstract	A two-sided rotation Jacobi SVD algorithm is used to compute the SVD and is implemented on a two million gate FPGA. A mesh-connected array structure is proposed based on Brent, Luk, and Van Loan's idea of an expandable square systolic array of simple 2x2 processors to compute the SVD of a large matrix, so as to shorten the iteration time and thus increase the implementation speed. The array consists of an n/2xn/2 array of 2x2 processor elements to compute the SVD of an nxn matrix. The trigonometric functions and the vector multiplication in the algorithm are tailored to the use of CORDIC (coordinate rotation digital computer) algorithms for hardware-efficient solutions. Two SVD processors, the basic SVD processor and the extended SVD processor, were developed. The algorithms to decompose the matrix were first evaluated in Matlab and then the processors were implemented using the Virtex-II FPGA from Xilinx as the target device. The basic SVD processor utilizes the proposed mesh-connected array structure and CORDIC algorithm. The implementation concentrates on utilizing the features of the FPGA to speed up operations and reduce the area required. In order to compute a large SVD without increasing the size of the FPGA, the extended SVD processor was developed to reuse the SVD array of the basic SVD processor. These two processors were successfully implemented on the FPGA device. Speed data and comparisons are presented
Starting Page	1047
Ending Page	1050
File Size	145292
Page Count	4
File Format	PDF
ISBN	1424400384
DOI	10.1109/CCECE.2006.277355
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-07
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Singular value decomposition Jacobian matrices Matrix decomposition Field programmable gate arrays Concurrent computing Systolic arrays Parallel processing Computer architecture Robustness Algebra fpga singular value decomposition jacobi
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An FPGA Implementation of the Hestenes-Jacobi Algorithm for Singular Value Decomposition

An Efficient Architecture for Floating-Point Eigenvalue Decomposition

Scalable parallel architecture for singular value decomposition of large matrices

Singular value decomposition FPGA implementation for tactile data processing

An FPGA-based floating-point Jacobi iterative solver

Assessment of FPGA Implementations of One Sided Jacobi Algorithm for Singular Value Decomposition

Reconfigurable FPGA-Based Unit for Singular Value Decomposition of Large m x n Matrices

Improved SVD systolic array and implementation on FPGA

Adaptive Jacobi method for parallel singular value decompositions

An FPGA-Based Singular Value Decomposition Processor

Similar Documents

An FPGA Implementation of the Hestenes-Jacobi Algorithm for Singular Value Decomposition

An Efficient Architecture for Floating-Point Eigenvalue Decomposition

Scalable parallel architecture for singular value decomposition of large matrices

Singular value decomposition FPGA implementation for tactile data processing

An FPGA-based floating-point Jacobi iterative solver

Assessment of FPGA Implementations of One Sided Jacobi Algorithm for Singular Value Decomposition

Reconfigurable FPGA-Based Unit for Singular Value Decomposition of Large m x n Matrices

Improved SVD systolic array and implementation on FPGA

Adaptive Jacobi method for parallel singular value decompositions

An FPGA-Based Singular Value Decomposition Processor