NDLI: Reconfigurable Implementation of Wavelet Transform on an Fpga-Augmented NIOS Processor

Content Provider	IEEE Xplore Digital Library
Author	Hyun, E. Sima, M. Mcguire, M.
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Victoria Univ., BC (Hyun, E.; Sima, M.; Mcguire, M.)
Abstract	The wavelet transform is a very popular tool in engineering for signal analysis. With respect to image compression, the new JPEG 2000 image standard incorporates wavelet transforms in its algorithm. Due to the high demands for processing and transmission, the trade-off of obtaining a high computation speed comes by sacrificing or reducing design flexibility. To meet the flexibility requirement, the discrete wavelet transform is implemented on an FPGA-augmented Nios processor. In particular, the lifting scheme is given reconfigurable-hardware support. To incorporate the newly defined lifting unit into the core processor, custom instructions are defined. This way, an ASIP-Nios can be defined on the fly at the expenses of FPGA utilization and custom instructions. Performance of the proposed design highlights significant speed improvement over a pure software implementation
Starting Page	1052
Ending Page	1055
File Size	4125904
Page Count	4
File Format	PDF
ISBN	1424400384
DOI	10.1109/CCECE.2006.277376
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-07
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wavelet transforms Discrete wavelet transforms Filter bank Hardware Field programmable gate arrays Wavelet analysis Frequency Software performance Signal resolution Low pass filters custom instruction Discrete Wavelet Transform lifting scheme FPGA Nios
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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