NDLI: Efficient CRT RSA with SCA Countermeasures

Content Provider	IEEE Xplore Digital Library
Author	Fournaris, A.P. Koufopavlou, O.
Copyright Year	2011
Abstract	RSA cryptographic algorithm, working as a security tool for many years, has long achieved cryptographic and market maturity. However, as all crypto algorithms, RSA implementations, after the discovery and wide spread of Side Channel Attacks (SCA), are susceptible to a wide variety of different attacks that target the hardware structure rather than the algorithm itself. While there are a wide range of countermeasures that can be applied on the RSA structure in order to protect the algorithm from SCAs, combining several such measures in order to guarantee an SCA resistant RSA design is not an easy job. There are many incompatibility issues among SCA protection methods as well as an extensive performance cost added to an SCA secure RSA implementation. In this paper, we address some very popular and potent SCAs against RSA like Fault attacks (FA), Simple Power attacks (SPA), Doubling attacks (DA) and Differential Power attacks (DPA), and propose an algorithmic modification of RSA based on Chinese Remainder Theorem (CRT) that can thwart those attacks. We describe an implementation approach based on Montgomery modular multiplication and propose a hardware architecture for a SCA resistant CRT RSA that is structured on our proposed algorithm. The designed architecture is imPublic Key Cryptography, VLSI Design, Side Channel Attack Resistance, Modular Exponentiation, plemented in FPGA technology and results on its time and space complexity are extracted and evaluated.
Starting Page	593
Ending Page	599
File Size	516432
Page Count	7
File Format	PDF
ISBN	9781457710483
DOI	10.1109/DSD.2011.81
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-08-31
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Cryptography Resistance Hardware Algorithm design and analysis Registers Computer architecture Modular Exponentiation Public Key Cryptography VLSI Design Side Channel Attack Resistance
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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