NDLI: SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems

Content Provider	IEEE Xplore Digital Library
Author	Straka, M. Kastil, J. Kotasek, Z.
Copyright Year	2011
Abstract	In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The framework is based on SEU generation outside FPGA (in personal computer) and the transport of modified bit stream through the JTAG interface and subsequent dynamic reconfiguration of FPGA. It allows to select region of the FPGA for SEU placing. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA. The requirements on the SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Virtex5 for different types of RTL circuits and fault tolerant architectures. The experimental results demonstrated the effectiveness of the methodology.
Starting Page	223
Ending Page	230
File Size	260277
Page Count	8
File Format	PDF
ISBN	9781457710483
DOI	10.1109/DSD.2011.32
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-08-31
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Generators Single event upset Fault tolerant systems Testing Tunneling magnetoresistance Computer architecture simulation SEU generator framework FPGA fault tolerant system partial reconfiguration testing
Content Type	Text
Resource Type	Article

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