NDLI: Architectures for Fast Modular Multiplication

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Table of Contents

Message from the Program Chair

Conference Committees

Human++: Key Challenges and Trade-offs in Embedded System Design for Personal Health Care (Abstract)

Human++: Key Challenges and Trade-offs in Embedded System Design for Personal Health Care

Cryptographic Contests: Toward Fair and Comprehensive Benchmarking of Cryptographic Algorithms in Hardware (Abstract)

The Future of Data-Parallel Embedded Systems (Abstract)

Generalized If-Then-Else Operator for Compact Polynomial Representation of Multi Output Functions

On the Cascade Implementation of Multiple-Output Sparse Logic Functions

On Failure Rate Assessment Using an Executable Model of the System

A Cost Effective Centralized Adaptive Routing for Networks-on-Chip

Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems

Numeral-Based Crosstalk Avoidance Coding to Reliable NoC Design

A Fast Congestion-Aware Flow Control Mechanism for ID-Based Networks-on-Chip with Best-Effort Communication

Optimal Selection of Function Implementation in a Hierarchical Configware Synthesis Method for a Coarse Grain Reconfigurable Architecture

VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs

PUMA: Placement Unification with Mapping and Guaranteed Throughput Allocation on an FPGA Using a Hardwired NoC

Improved Power Modeling of DDR SDRAMs

Path-Based Dynamic Voltage and Frequency Scaling Algorithms for Multiprocessor Embedded Applications with Soft Delay Deadlines

Power Minimisation for Real-Time Dataflow Applications

VHDL Code Generation from Formal Event-B Models

Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage

Hardware Reuse in Modern Application-Specific Processors and Accelerators

Quaternary High Performance Arithmetic Logic Unit Design

Low-Latency and Low-Overhead Mesochronous and Plesiochronous Synchronizers

Towards an Efficient NoC Topology through Multiple Injection Ports

LastZ: An Ultra Optimized 3D Networks-on-Chip Architecture

Comparison of Different Thread Scheduling Strategies for Asymmetric Chip MultiThreading Architectures in Embedded Systems

SAT-Based Generation of Compressed Skewed-Load Tests for Transition Delay Faults

Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation

Chip Temperature Selfregulation for Digital Circuits Using Polymorphic Electronics Principles

A Technique for Accelerating Injection of Transient Faults in Complex SoCs

SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems

Fault Tolerance of Multiple Logic Faults in SRAM-Based FPGA Systems

Reliability-Aware Design Optimization for Multiprocessor Embedded Systems

Design of Asynchronous Circuits on FPGAs for Soft Error Tolerance

HMMER Performance Model for Multicore Architectures

Kactus2: Environment for Embedded Product Development Using IP-XACT and MCAPI

10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard

Multicore Cache Simulations Using Heterogeneous Computing on General Purpose and Graphics Processors

Power Spectral Density Side Channel Attack Overlapping Window Method

Dynamic Power Estimation for Motion Estimation Hardware

A Module for Packet Hijacking in NetFPGA Platform

Fault Models Usability Study for On-line Tested FPGA

Hardware Implementation of a Flexible Tag Platform for Passive RFID Devices

Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder

An Overlapped Block Motion Compensation Hardware for Frame Rate Conversion

Cost of Sparse Mesh Layouts Supporting Throughput Computing

An Environment for (re)configuration and Execution Managenment of Flexible Radio Platforms

FBMC and GFDM Interference Cancellation Schemes for Flexible Digital Radio PHY Design

A Novel Architecture for Scalable, High Throughput, Multi-standard LDPC Decoder

A Non-Intrusive Online FPGA Test Scheme Using a Hardwired Network on Chip

Techniques for SAT-Based Constrained Test Pattern Generation

On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits

An Enhanced Path Delay Fault Simulator for Combinational Circuits

Dynamic Soft Error Hardening via Joint Body Biasing and Dynamic Voltage Scaling

Design of Fault Tolerant Network Interfaces for NoCs

Designing Robust Asynchronous Circuits Based on FinFET Technology

Analyzing Area Penalty of 32-Bit Fault Tolerant ALU Using BCH Code

Low Power FPGA Implementations of JH and Fugue Hash Functions

Mutant Fault Injection in Functional Properties of a Model to Improve Coverage Metrics

A Unified Architecture for BCD and Binary Adder/Subtractor

Synthesizing Concurrent Synchronous Computing Machines from Interrupt-Driven Binaries

Architectures for Fast Modular Multiplication

Transaction Level Modeling of a Networked Embedded System Based on a Power Line Communication Protocol

Nexus: Hardware Support for Task-Based Programming

Evaluation of Fault-Tolerant Routing Methods for NoC Architectures

On the Design of Modulo 2^n+1 Multipliers

Binary-to-RNS Conversion Units for moduli {2^n ± 3}

Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion

Automated Design Debugging in a Testbench-Based Verification Environment

Efficient Fault Simulation of SystemC Designs

Higher-Order Abstraction in Hardware Descriptions with C?aSH

Thermal Effect of TSVs in 3D Die-Stacked Integrated Circuits

A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations

Dynamic Flow Reconfiguration Strategy to Avoid Communication Hot-Spots

Microthreading as a Novel Method for Close Coupling of Custom Hardware Accelerators to SVP Processors

Pre-silicon Characterization of NIST SHA-3 Final Round Candidates

Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms

Modular Fault Injector for Multiple Fault Dependability and Security Evaluations

Breaking Hitag2 with Reconfigurable Hardware

Iteration-Based Trade-Off Analysis of Resource-Aware SDF

SoC and Board Modeling for Processor-Centric Board Testing

Hybrid Code-Data Prefetch-Aware Multiprocessor Task Graph Scheduling

Efficient CRT RSA with SCA Countermeasures

Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level

HDL-Mutation Based Simulation Data Generation by Propagation Guided Search

On-chip Monitoring: A Light-Weight Interconnection Network Approach

Enhancing Performance Sustainability of Fault Tolerant Routing Algorithms in NoC-Based Architectures

Formal Modeling of Multicast Communication in 3D NoCs

Thermal Analysis of Job Allocation and Scheduling Schemes for 3D Stacked NoC's

A Configurable Ring-Oscillator-Based PUF for Xilinx FPGAs

A Unified Multiply/Accumulate Unit for Pairing-Based Cryptography over Prime, Binary and Ternary Fields

A Novel Architecture of Implementing Error Detecting AES Using PRNS

How a Symmetry Metric Assists Side-Channel Evaluation - A Novel Model Verification Method for Power Analysis

Rapid and Accurate Leakage Power Estimation for Nano-CMOS Circuits

An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating

A Design Method for Programmable Two-Variable Discrete Function Generators Using Spline and Bilinear Interpolations

Exploiting Inter and Intra Application Dynamism to Save Energy

Model Driven Cache-Aware Scheduling of Object Oriented Software for Chip Multiprocessors

Compiling Esterel for Multi-core Execution

Phase-Guided Scheduling on Single-ISA Heterogeneous Multicore Processors

Energy Behaviour of NUCA Caches in CMPs

A Wearable Intelligent System for the Health of Expectant Mom's and of Their Children

Embedded System for Camera-Based TV Power Reduction

An Embedded Video Sensor for a Smart Traffic Light

On the Efficiency of Design Time Evaluation of the Resistance to Power Attacks

Soft Error Detection Technique in Multi-threaded Architectures Using Control-Flow Monitoring

Automatic Interface Generation for Component Reuse in HW-SW Partitioning

A Scalable Distributed Asynchronous Control Network for High Level Synthesis of Digital Circuits

A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers

Faster Processor Allocation Algorithms for Mesh-Connected CMPs

Compatibility Study of Compile-Time Optimizations for Power and Reliability

An FPGA Implementation of the ZUC Stream Cipher

A Unified Execution Model for Data-Driven Applications on a Composable MPSoC

Publisher's Information

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)

9th EUROMICRO Conference on Digital System Design (DSD'06)

8th Euromicro Conference on Digital System Design (DSD'05)

Euromicro Symposium on Digital System Design, 2004. DSD 2004.

Euromicro Symposium on Digital System Design, 2003. Proceedings.

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools

Proceedings Euromicro Symposium on Digital Systems Design

Architectures for Fast Modular Multiplication

Content Provider	IEEE Xplore Digital Library
Author	Aris, A. Ors, B. Saldamli, G.
Copyright Year	2011
Abstract	Modular multiplication is the key ingredient needed to realize most public-key cryptographic primitives. In a modular setting, multiplications are carried in two steps: namely a usual integer arithmetic followed by a reduction step. Progress in any of these steps naturally improves the modular multiplication but it is not possible to interleave the best algorithms of these stages. In this study, we propose architectures for recently proposed method of interleaving the Karatsuba-Ofman multiplier and bipartite modular reduction on the upper most layer of Karatsuba-Ofman's recursion. We manage to come up with a high performance modular multiplication architecture by taking the advantage of a fast multiplication and a parallel reduction method.
Starting Page	434
Ending Page	437
File Size	261742
Page Count	4
File Format	PDF
ISBN	9781457710483
DOI	10.1109/DSD.2011.60
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-08-31
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Hardware Elliptic curve cryptography Computer architecture Registers Signal processing algorithms interleaved multiplication Bipartite modular multiplication Karatsuba-Ofman Algorithm modular arithmetic
Content Type	Text
Resource Type	Article

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