NDLI: Verilog-A and Verilog-AMS provides a new dimension in modeling and simulation

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Verilog-A and Verilog-AMS provides a new dimension in modeling and simulation

Content Provider	IEEE Xplore Digital Library
Author	Miller, I. Cassagnes, T.
Copyright Year	2000
Description	Author affiliation: Motorola ESD Europe, Chandler, AZ, USA (Miller, I.)
Abstract	Verilog-A provides a new dimension in modeling, design and simulation capability for analog and mixed signal electronic systems. Previously, analog simulation has been based upon Spice, which is a very effective simulation environment based on primitives such as transistors, resistors, and capacitors. Digital design verification is based on a Hardware Description Language (HDL). Verilog and Verilog derivatives have been widely accepted due to their ease of use and gate level simulation capability. Verilog, which accounted for more than 60% of the HDL simulator sales in 1997, has a strong following with a host of tools that complement the language and extend the capability to verification and test. This paper presents the motivation for the Verilog-A language, an extension of Verilog to describe analog and non-electrical behavior, and illustrates the Verilog-A language via short examples and a overview of an ink jet printer ASIC support IC behavioral model.
File Size	425745
File Format	PDF
ISBN	0780357663
DOI	10.1109/ICCDCS.2000.869811
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-03-17
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware design languages Integrated circuit modeling Signal design Resistors Capacitors Marketing and sales Testing Ink jet printing Application specific integrated circuits Analog integrated circuits
Content Type	Text
Resource Type	Article

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