NDLI: Method of modeling analog circuits in verilog for mixed-signal design simulations

Content Provider	IEEE Xplore Digital Library
Author	Wegener, C.
Copyright Year	2013
Description	Author affiliation: Corp. Eng., Dialog Semicond. GmbH, Germering, Germany (Wegener, C.)
Abstract	Simulating mixed-signal circuit designs needs to bridge between the analog and digital circuit domains. Preserving the behavior and structure of the analog and digital parts of the circuit is possible with Hardware Description Languages (HDLs), such as Verilog-AMS. However, the analog and digital parts of the design are typically developed in simulation environments tailored to either the analog or digital design flow requirements. For digital circuit development, Verilog is a popular choice of HDL. Including the analog part of the mixed-signal circuit in the Verilog description without the AMS extension requires a modeling strategy that can preserve fundamental analog behavior. In this contribution we describe a method of modeling analog sub-circuits in Verilog. The higher-level analog circuit is modeled by netlisting the connectivity of sub-circuits based on a schematic. This method of modeling and hierarchical netlisting is scalable and demonstrated for the example of an Analog-to-Digital Converter (ADC). We can simulate the digital design interacting with the analog circuit on any standard Verilog simulator, thus, (proprietary) language extensions are not required.
Starting Page	1
Ending Page	5
File Size	197247
Page Count	5
File Format	PDF
ISBN	9783000437854
DOI	10.1109/ECCTD.2013.6662227
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-08
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	TU Dresden
Subject Keyword	Solid modeling Capacitors Switches Analog circuits Mathematical model Hardware design languages Integrated circuit modeling
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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