NDLI: Synthesis for manufacturability: a sanity check

Content Provider	IEEE Xplore Digital Library
Author	Nardi, A. Sangiovanni-Vincentelli, A.L.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA (Nardi, A.; Sangiovanni-Vincentelli, A.L.)
Abstract	As we move towards nanometer technology, manufacturing problems become overwhelmingly difficult to solve. Presently, optimization for manufacturability is performed at a post-synthesis stage and has been shown capable of reducing manufacturing cost up to 10%. As in other cases, raising the abstraction layer where optimization is applied is expected to yield substantial gains. This paper focuses on a new approach to design for manufacturability: logic synthesis for manufacturability. This methodology consists of replacing the traditional area-driven technology mapping with a new manufacturability-driven one. We leverage existing logic synthesis tools to test our method. The results obtained by using STMicroelectronics 0.13 /spl mu/m library confirm that this approach is a promising solution for designing circuits with lower manufacturing cost, while retaining performance. Finally, we show that our synthesis for manufacturability can achieve even larger cost reduction when yield-optimized cells are added to the library, thus enabling a wider area-yield tradeoff exploration.
Sponsorship	EDAA, EDA Consortium, IEEE Comput. Soc. TTTC IEEE Comput. Soc. DATC ECSI ACM/SIGDA RAS
Starting Page	796
Ending Page	801
File Size	346273
Page Count	6
File Format	PDF
ISBN	0769520855
ISSN	15301591
DOI	10.1109/DATE.2004.1268978
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-02-16
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Cost function Circuit synthesis Manufacturing processes Design optimization Pulp manufacturing Logic testing Libraries Design for manufacture Logic design Circuit testing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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