NDLI: Phase coupled code generation for DSPs using a genetic algorithm

Content Provider	IEEE Xplore Digital Library
Author	Lorenz, M. Marwedel, P.
Copyright Year	2004
Description	Author affiliation: Dept. of Comput. Sci., Dortmund Univ., Germany (Lorenz, M.; Marwedel, P.)
Abstract	The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. Due to the irregular architectures present in today's DSPs there is a need of compilers which are capable of performing a phase coupling of the highly interdependent code generation subtasks and a graph based code selection. In this paper we present a code generator which performs a graph based code selection and a complete phase coupling of code selection, instruction scheduling (including compaction) and register allocation. In addition, our code generator takes into account effects of the subsequent address code generation phase. In order to solve the phase coupling problem and to handle the problem complexity, our code generator is based on a genetic algorithm. Experimental results for several benchmarks and an MP3 application for two DSPs show the effectiveness and the retargetability of our approach. Using the presented techniques, the number of execution cycles is reduced by 51 % on average for the M3-DSP and by 38% on average for the ADSP2100 compared to standard techniques.
Sponsorship	EDAA, EDA Consortium, IEEE Comput. Soc. TTTC IEEE Comput. Soc. DATC ECSI ACM/SIGDA RAS
Starting Page	1270
Ending Page	1275
File Size	931054
Page Count	6
File Format	PDF
ISBN	0769520855
ISSN	15301591
DOI	10.1109/DATE.2004.1269070
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-02-16
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processing Genetic algorithms Registers Tree graphs Energy consumption Digital signal processors Embedded system Optimizing compilers Compaction Assembly
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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