NDLI: Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering

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DAC '93 [Cover page]

DAC'93 Title Page

DAC'93 Copyright Page

Executive Committee

General Chair's Message

Technical Program Committee

Call for Papers

Table of contents

1993 Keynote Address

An Efficient Critical Race-Free State Assignment Technique for Asynchronous Finite State Machines

Elimination of Dynamic Hazards by Factoring

Optimized State Assignment of Single Fault Tolerant FSMs Based on SEC Codes

Minimal Shift Counters and Frequency Division

Algorithms for Approximate FSM Traversal

SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm

Resistance Extraction Using a Routing Algorithm

HV/VH Trees: A New Spatial Data Structure for Fast Region Queries

Increasing Design Quality and Engineering Productivity through Design Reuse

Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping

Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs

Technology Decomposition and Mapping Targeting Low Power Dissipation

Technology Mapping for Low Power

INCREDYBLE-TG: INCREmental DYnamic Test Generation Based on LEarning

Automatic Functional Test Generation Using The Extended Finite State Machine Model

Speed up of Behavioral A.T.P.G. Using a Heuristic Criterion

A State Traversal Algorithm Using a State Covariance Matrix

Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits

Sequential Circuit Test Generation on a Distributed System

VIPER: An Efficient Vigorously Sensitizable Path Extractor

A Polynomial-Time Heuristic Approach to Approximate a Solution to the False Path Problem

A Verification Technique for Gated Clock

Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions

Timing Optimization by Gate Resizing and Critical Path Identification

Panel: What Is the Next Big Productivity Boost for Designers?

Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances

A New Optimizer for Performance Optimization of Analog Integrated Circuits

Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits

Analog System Verification in the Presence of Parasitics Using Behavioral Simulation

Panel: Logic Emulation: A Niche or a Future Standard for Design Verification?

Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization

Performance Oriented Rectilinear Steiner Trees

Performance-Driven Steiner Tree Algorithms for Global Routing

High-Performance Routing Trees with Identified Critical Sinks

The Sea-of-Wires Array Synthesis System

Experiences in Functional Validation of a High Level Synthesis System

An Efficient Method of Partitioning Circuits for Multiple-FPGA Implementation.

Performance Directed Technology Mapping for Look-Up Table Based FPGAs

On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping

MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs

Sequential Synthesis for Table Look Up Programmable Gate Arrays

Routability-Driven Fanout Optimization

Non-Scan Design-for-Testability Techniques for Sequential Circuits

An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing

Partial Scan with Retiming

A Cost-Based Approach to Partial Scan

On Computing the Transitive Closure of a State Transition Relation

Reducing BDD Size by Exploiting Functional Dependencies

Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems

Information Modelling of EDIF

Panel: Life Expectancy of Standards

A Layout Estimation Algorithm for RTL Datapaths

Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments

Utilization of Multiport Memories in Data Path Synthesis

Architectural Synthesis of Performance--Driven Multipliers with Accumulator Interleaving

Panel: Embedded Systems and Hardware-Software Co-Design: Panacea or Pandora's Box?

Optimal Clustering for Delay Minimization

Cost Minimization of Partitions into Multiple Devices

Iterative Wirability and Performance Improvement for FPGAs

On Routability Prediction for Field-Programmable Gate Arrays

The Clinton/Gore Technology Policies

High-Level Synthesis of Scalable Architectures for IIR Filters Using Multichip Modules

An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition

InSyn: Integrated Scheduling for DSP Applications

Estimating Architectural Resources and Performance for High-Level Synthesis Applications

Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering

Evaluation by Parts of Mixed-Level DC-Connected Components in Logic Simulation

Comparative Design Validation Based on Event Pattern Mappings

Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects

Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits

MSTC: A Method for Identifying Overconstraints during Hierarchical Compaction

Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP

Optimal Graph Constraint Reduction for Symbolic Layout Compaction

A Compaction Method for Full Chip VLSI Layouts

High-Level Transformations for Minimizing Syntactic Variances

An Approach for Redesigning in Data Path Synthesis

High-level Symbolic Construction Techniques for High Performance Sequential Synthesis

High-Level Synthesis of Fault-Secure Microarchitectures

Towards Optimal System-Level Design

NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits

Delay Fault Coverage and Performance Tradeoffs

Design for Testability for Path Delay Faults in Sequential Circuits

Bridge Fault Simulation Strategies for CMOS Integrated Circuits

Minimum Length Synchronizing Sequences of Finite State Machine

Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving

A Unified Approach to Language Containment and Fair CTL Model Checking

Panel: Are EDA Platform Preferences About to Shift

Sequential Circuit Delay Optimization Using Global Path Delays

Resynthesis of Multi-Phase Pipelines

TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry

Diagnosis and Correction of Logic Design Errors in Digital Circuits

DRAFTS: Discretized Analog Circuit Fault Simulator

Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy

An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits

A Bounded 2D Contour Searching Algorithm for Floorplan Design with Arbitrarily Shaped Rectilinear and Soft Modules

Prime: A Timing-Driven Placement Tool Using A Piecewise Linear Resistive Network Approach

A Buffer Distribution Algorithm for High-Speed Clock Routing

Cooperative Approach to a Practical Analog LSI Layout System

Selective Pseudo Scan - Combinational Atpg with Reduced Scan in a Full Custom Risc Microprocessor

ABLE: AMD Backplane for Layout Engines

Practical Statistical Design of Complex Integrated Circuit Products

Rotation Scheduling: A Loop Pipelining Algorithm

Critical Path Minimization Using Retiming and Algebraic Speed-Up

A Tree-Based Scheduling Algorithm for Control-Dominated Circuits

Synthesis of Pipelined Instruction Set Processors

Panel: Military to Commercial Conversion: Is it Necessary, Is it Practical, Is it Possible?

An Efficient Multilayer MCM Router Based on Four-Via Routing

An Efficient Timing-Driven Global Routing Algorithm

A Negative Reinforcement Method for PGA Routing

Performance-Driven Interconnect Design Based on Distributed RC Delay Model

A Clustering-Based Optimization Algorithm in Zero-Skew Routings

Panel: Multi-vendor Tool Integration Experiences

ESPRESSO-SIGNATURE: A New Exact Minimizer for Logic Functions

A New Viewpoint on Two-Level Logic Minimization

Optimization of Combinational Logic Circuits Based on Compatible Gates

Optimization and Resynthesis of Complex Data-Paths

BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis

Design Management Using Dynamically Defined Flows

Active Documentation: a New Interface for VLSI Design

Performance Specification Using Attributed Grammars

An Information Model of Time

A Cross-Debugging Method for Hardware/Software Co-design Environments

FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program

High-Speed Interconnect Modeling and High-Accuracy Simulation Using SPICE and Finite Element Methods

Fast Approximation of the Transient Response of Lossy Transmission Line Trees

Analysis and Reliable Design of ECL Circuits with Distributed RLC Interconnections

Frequency Domain Microwave Modeling Using Retarded Partial Element Equivalent Circuits

The State of CAD and VLSI in Russia

The State of VHDL in Russia

The State of Simulation in Russia

The State of EDA in Russian Universities

An Efficient Non-Quasi-Static Diode Model for Circuit Simulation

S-Parameter Based Macro Model of Distributed-Lumped Networks Using Exponentially Decayed Polynomial Function

Addressing High-speed Interconnect Issues in Asymptotic Waveform Evaluation

Incremental Event-Driven Simulation of Digital FET Circuits

Panel: Where in the World Should CAD Software be Made?

Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning

Spectral K-Way Ratio-Cut Partitioning and Clustering

A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design

Quadratic Boolean Programming for Performance-Driven System Partitioning

Panel: The Key to EDA Results: Component & Library Management

Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering

Content Provider	IEEE Xplore Digital Library
Author	Carlson, B.S. Chen, C.Y.R.
Copyright Year	1993
Description	Author affiliation: The Advanced IC Design and Simulation Laboratory and the Department of Electrical Engineering, State University of New York, Stony Brook, NY (Carlson, B.S.)
Abstract	A method which uses transistor reordering for the performance enhancement of CMOS circuits is presented. The proposed technique achieves significant reduction in propagation delays with little effect on layout area. The technique can be coupled with transistor sizing to achieve unbounded improvement in circuit delay, and it can be used to decrease dynamic power dissipation. In particular, excellent results have been achieved when the method is applied to data path circuits.
Starting Page	361
Ending Page	366
File Size	381237
Page Count	6
File Format	PDF
ISBN	0897915771
ISSN	0738100X
DOI	10.1109/DAC.1993.203975
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-06-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Very large scale integration Propagation delay Transistors Switches Switching circuits Logic gates CMOS logic circuits Logic devices Registers Delay effects
Content Type	Text
Resource Type	Article

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