NDLI: High-Level Synthesis of Scalable Architectures for IIR Filters Using Multichip Modules

Content Provider	IEEE Xplore Digital Library
Author	Haigeng Wang Dutt, Nikil Nicolau, A. Kai-Yeung Sunny Siu
Copyright Year	1993
Description	Author affiliation: Department of Computer Science, University of California, Irvine, Irvine, CA (Haigeng Wang)
Abstract	We present a new technique for the high-level synthesis of scalable MCM-based architectures implementing infinite-impulse response(IIR) filters. Our technique is based on the regular schedules, a class of parallel schedules for computing mth-order IIR filters. The simplicity of the regular schedules facilitates characterization of their inter-processor communications, which is generally difficult to express for parallel algorithms. The characterization of inter-processor communications of the regular schedules enables us to generate instruction-level behavior of the design that can be easily mapped onto MCM-based architectures. We illustrate this mapping of the regular schedules onto an MCM-based architecture by designing a special-purpose processor for the fifth-order elliptic wave filter. Our design yields a scalable performance measured in the filter's sample rate, which is not known to have been achieved by previously published designs. This work differs significantly from "traditional" high-level synthesis techniques in its emphasis on synthesizing scalable, high-performance multichip designs.
Starting Page	336
Ending Page	342
File Size	640056
Page Count	7
File Format	PDF
ISBN	0897915771
ISSN	0738100X
DOI	10.1109/DAC.1993.203971
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-06-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	High level synthesis IIR filters Multichip modules Processor scheduling Computer architecture Concurrent computing Difference equations Parallel processing Signal synthesis Signal processing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Regular schedules for scalable design of IIR filters

High-level synthesis of scalable architectures for IIR filters using multichip modules

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High-Level Synthesis of Scalable Architectures for IIR Filters Using Multichip Modules (1992)

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