NDLI: Functional Simulation Shortens the Development Cycle of a New Computer

Content Provider	IEEE Xplore Digital Library
Author	Cheng, R. Griffin, B. Katsumata, K. Welsh, J.
Copyright Year	1983
Abstract	A high-performance VLSI CPU subsystem for an Ada-oriented 32-bit Instruction Set Architecture was effectively designed and validated on a short schedule using the ISP' hardware descriptive language and N.mPc functional simulation tools. The architecture employs a horizontal microcode structure that drives numerous parallel hardware functions to achieve a throughput performance approaching 3 mips. The design approach incorporated construction of individual ISP' models and simulation of the total system to ensure the functional correctness of the total architecture, the VLSI device partitions, and the detailed interfaces. Additionally, firmware for the complete instruction set was produced and verified by means of simulation on the models. The effectiveness of this approach is evidenced by the efficient CPU functional design and validation work and the rapid integration of the microcode on an advanced development model of the system. The success of this design approach has been a key factor in meeting the development schedule.
Starting Page	515
Ending Page	519
File Size	547131
Page Count	5
File Format	PDF
ISBN	0818600268
ISSN	0738100X
DOI	10.1109/DAC.1983.1585701
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1983-06-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computational modeling Computer simulation Very large scale integration Hardware Processor scheduling Computer architecture Circuit simulation Computer aided instruction Service oriented architecture Microprogramming
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

VHDL: software based hardware designs

A hardware processor for implementing the pyramid vector quantizer

A Micro-architecture Simulator for Multimedia Stream Processor

Hierarchical Architecture Design and Simulation Environment

A Ubiquitous Processor Free from Instruction Scheduling

A new approach to pipeline FFT processor

A Simulation Environment for Microprocessor Architecture Evaluation

RT-Level Deviation-Based Grading of Functional Test Sequences

Scheduling for an Embedded Architecture with a Flexible Datapath

Functional Simulation Shortens the Development Cycle of a New Computer

Similar Documents

VHDL: software based hardware designs

A hardware processor for implementing the pyramid vector quantizer

A Micro-architecture Simulator for Multimedia Stream Processor

Hierarchical Architecture Design and Simulation Environment

A Ubiquitous Processor Free from Instruction Scheduling

A new approach to pipeline FFT processor

A Simulation Environment for Microprocessor Architecture Evaluation

RT-Level Deviation-Based Grading of Functional Test Sequences

Scheduling for an Embedded Architecture with a Flexible Datapath

Functional Simulation Shortens the Development Cycle of a New Computer