NDLI: On-chip interconnect-aware design and modeling methodology based on high bandwidth transmission line devices

Content Provider	IEEE Xplore Digital Library
Author	Goren, D. Zelikson, M. Gordin, R. Wagner, I.A. Barger, A. Amir, A. Livshitz, B. Sherman, A. Tretiakov, Y. Groves, R. Park, J. Jordan, D. Strang, S. Singh, R. Dickey, C. Harame, D.
Copyright Year	2003
Description	Author affiliation: IBM Haifa R&D Labs, Israel (Goren, D.; Zelikson, M.; Gordin, R.; Wagner, I.A.; Barger, A.; Amir, A.; Livshitz, B.; Sherman, A.)
Abstract	This paper expands the on-chip interconnect-aware methodology for high-speed analog and mixed signal design, presented in D. Goren et al. (2002), into a wider class of designs, including dense layout CMOS design. The proposed solution employs a set of parameterized on-chip transmission line (T-line) devices for the critical interconnects, which is expanded to include coplanar structures while considering the silicon substrate effect. The generalized methodology contains treatment of the crossing line effects at the various design stages, including two way interactions between the post layout extraction tool and the T-line devices. The T-line device models are passive by construction, easily migratable among design environments, and allow for both time and frequency domain simulations. These models are verified by S-parameter measurements up to 110GHz, as well as by EM solver results. It is experimentally shown that the effect of properly designed discontinuities is negligible in most practical cases. The basic on-chip T-line methodology is being used extensively for numerous high-speed designs.
Starting Page	724
Ending Page	727
File Size	394428
Page Count	4
File Format	PDF
ISBN	1581136889
DOI	10.1109/DAC.2003.1219114
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-06-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Design methodology Bandwidth Transmission lines Integrated circuit interconnections Signal design Integrated circuit measurements Permission Impedance Research and development Silicon germanium
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Interconnect-aware design methodology for analog and mixed signal design in silicon based technologies using high bandwidth on-chip transmission lines

An interconnect-aware methodology for analog and mixed signal design, based on high bandwidth (over 40 GHz) on-chip transmission line approach

On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices

High-density silicon carrier transmission line design for chip-to-chip interconnects

On-chip Interconnect-Aware Design and Modeling Methodology, Based on High Bandwidth Transmission Line Devices

Optimising broadband signal transfer across long on–chip interconnect

A new on-wafer de-embedding technique for on-chip rf transmission line interconnect characterization

Modeling of On-Chip Transmission Lines in High-Speed A&MS Design - The Low Frequency Inductance Calculation

High-speed on-chip interconnect modeling for circuit simulation

On-chip interconnect-aware design and modeling methodology based on high bandwidth transmission line devices

Similar Documents

Interconnect-aware design methodology for analog and mixed signal design in silicon based technologies using high bandwidth on-chip transmission lines

An interconnect-aware methodology for analog and mixed signal design, based on high bandwidth (over 40 GHz) on-chip transmission line approach

On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices

High-density silicon carrier transmission line design for chip-to-chip interconnects

On-chip Interconnect-Aware Design and Modeling Methodology, Based on High Bandwidth Transmission Line Devices

Optimising broadband signal transfer across long on–chip interconnect

A new on-wafer de-embedding technique for on-chip rf transmission line interconnect characterization

Modeling of On-Chip Transmission Lines in High-Speed A&MS Design - The Low Frequency Inductance Calculation

High-speed on-chip interconnect modeling for circuit simulation

On-chip interconnect-aware design and modeling methodology based on high bandwidth transmission line devices