NDLI: Test cost reduction for SOCs using TAMs and Lagrange multipliers

Content Provider	IEEE Xplore Digital Library
Author	Sehgal, A. Iyengar, V. Krasniewski, M.D. Chakrabarty, K.
Copyright Year	2003
Description	Author affiliation: Electr. & Comput. Eng., Duke Univ., Durham, NC, USA (Sehgal, A.)
Abstract	Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically run at lower frequencies (10-50 MHz). The use of high-speed ATE channels to drive slower scan chains leads to an underutilization of resources, thereby resulting in an increase in testing time. We present a new technique to reduce the testing time and test cost by matching high-speed ATE channels to slower scan chains using the concept of virtual test access mechanisms (TAMs). We also present a new TAM optimization framework based in Lagrange multipliers. Experimental results are presented for three industrial circuits from the ITC'02 SOC test benchmarks.
Starting Page	738
Ending Page	743
File Size	786391
Page Count	6
File Format	PDF
ISBN	1581136889
DOI	10.1109/DAC.2003.1219117
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-06-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Costs Lagrangian functions Circuit testing Automatic testing Automatic test equipment System-on-a-chip Integrated circuit testing System testing Permission Investments
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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