NDLI: Analysis and minimization techniques for total leakage considering gate oxide leakage

Content Provider	IEEE Xplore Digital Library
Author	Lee, D. Kwong, W. Blaauw, D. Sylvester, D.
Copyright Year	2003
Description	Author affiliation: Univ. of Michigan, Ann Arbor, MI, USA (Lee, D.; Kwong, W.; Blaauw, D.; Sylvester, D.)
Abstract	In this paper we address the growing issue of gate oxide leakage current (I/sub gate/) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I/sub gate/ and subthreshold leakage (I/sub sub/). The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on table look-ups to quickly estimate the state-dependent total leakage current within 1% of SPICE. We then make several observations on the impact of I/sub gate/ in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR vs. NAND topologies. Based on these observations, we propose the use of pin recording as a means to reduce I/sub gate/ due to the dependencies of gate leakage on stack node voltages.
Starting Page	175
Ending Page	180
File Size	784787
Page Count	6
File Format	PDF
ISBN	1581136889
DOI	10.1109/DAC.2003.1218934
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-06-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Leakage current MOS devices Voltage Tunneling Circuits CMOS technology Permission National electric code Minimization Subthreshold current
Content Type	Text
Resource Type	Article

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