NDLI: High-speed on-chip interconnect modeling for circuit simulation

Content Provider	IEEE Xplore Digital Library
Author	Caputa, P. Alvandpour, A. Svensson, C.
Copyright Year	2004
Description	Author affiliation: Electronic Devices Group, Dept. of EE, Linkoping University, SE-581 83 Linkoping, Sweden (Caputa, P.; Alvandpour, A.; Svensson, C.)
Abstract	We investigate the relevance of inductance in interconnect models through simulation of an on-chip bus described by a HSPICE W-element, a RLC-network, and a RC-network, respectively. For worst-case delay estimations, we show that the simplest RC-model h sufficient. We further demonstrate the importance of including inductance in noise and edge-rate simulations. For the longest interconnect investigated, the W-element and RC-network differ by 20.6% in overshoot, 156% in ground noise, 53.2% in crosstalk and 61.7% in edge-rule simulations. The W-element and RLC-network never diverge by more than 2% in overshoot, 12.4% in ground noise, 8.9% in crosstalk and 5.6% in edge-rate simulations.
Starting Page	143
Ending Page	146
File Size	271136
Page Count	4
File Format	PDF
ISBN	0780385101
DOI	10.1109/NORCHP.2004.1423843
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-11-08
Publisher Place	Norway
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit simulation global interconnect Integrated circuit interconnections Crosstalk RLC circuits lossy transmission lines Multiconductor transmission lines Wire Delay Inductance signal integrity on-chip interconnect modeling Distributed parameter circuits Capacitance
Content Type	Text
Resource Type	Article

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