NDLI: Domain-specific high-level modeling and synthesis for ATM switch design using VHDL

Content Provider	IEEE Xplore Digital Library
Author	Mike Tien-Chien Lee Yu-Chin Hsu Ben Chen Fujita, M.
Copyright Year	1996
Description	Author affiliation: Fujitsu Labs. of America, Santa Clara, CA, USA (Mike Tien-Chien Lee)
Abstract	This paper presents our experience on domain-specific high-level modeling and synthesis for Fujitsu ATM switch design. We propose a high-level design methodology using VHDL, where ATM switch architectural features are considered during behavior modeling, and a high-level synthesis compiler, MEBS, is prototyped to synthesize the behavior model down to a gate-level implementation. Since the specific ATM switch architecture is incorporated into both modeling and syntheses phases, a high-quality design is efficiently derived. The synthesis results show that given the design constraints, the proposed high-level design methodology can produce a gate-level implementation by MEBS with about 15% area reduction in shorter design cycle when compared with manual design.
Starting Page	585
Ending Page	590
File Size	798901
Page Count	6
File Format	PDF
ISBN	0780332946
ISSN	0738100X
DOI	10.1109/DAC.1996.545643
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-06-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Asynchronous transfer mode High level synthesis Permission Design methodology Packet switching Communication switching Design automation Clocks Laboratories
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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